[SOLVED] Cadence LVS Net-list Ambiguities

I'm having LVS trouble implementing a simple ripple-carry adder in Cadence. I'm building a 21-bit RCA using full adder and inverter standard cells I built previously. I have already used these cells in other designs without issue. For some reason with the RCA I'm getting "net-list ambiguities were resolved by random selection" for many of my A and B inputs that feed into the full adders.

termbad.out:
T -1 in_a0 / in_a0
? Terminal in_a0 in the layout is matched to terminal in_b0 in the schematic.
T -1 in_b0 / in_b0
? Terminal in_b0 in the layout is matched to terminal in_a0 in the schematic.
etc...

The nets appear to be correct in the extracted view. I've tried swapping the inputs in the layout, which still results in the same error message. Swapping the inputs in the schematic, however, correct the problem. The kicker is, not all of the inputs need to be swapped (bit 0 generates an error but bit 4 does not).

I've been pulling my hair out over this for hours now. Does anyone have an idea what this might indicate?

After generating the extracted view, open the extracted view and in the run LVS dialog box click on errors. A new dialog box opens showing the errors encountered. For each error, you can see the nets highlighted in yellow in the extracted view. Check these highlighted nets in the layout and schematic for connectivity mistakes. Hopefully you can figure out your mistakes.

The problem appears to be with symmetry. Since the A and B circuits are equivalent in my full adder design I tried adding an inverter to the A line, which resolves the error. I'm unclear why I haven't had an issue with this before, however. Any ideas?

I dont understand what you mean here by symmetry and "A and B circuits being equivalent". Its possible that I misunderstood what you meant. Can you please be more descriptive?

Not sure if this will be legible, but the pull up and pull down networks for my full adder are symmetric. In this design the A and B inputs are equivalent.

I dont understand one thing here. You say that its a 21 bit RCA. But you have a single bit input for A and B. How does that work?
Shouldnt the inputs A and B be 21 bit inputs?

I posted the full adder schematic since that highlights the symmetry across the A and B inputs. The is the 21-bit RCA schematic employing alternating logic.



Note the inverter output added at bit 0 to break the symmetry. This corrects the LVS error for that bit position, however, the other 20 bits are still resolved by random selection.

Turns out the problem was with modifications that someone else had made to the NCSU design kit (and not the circuit or the tool).