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[SOLVED] Need Clock Gating Design advice

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Rogov

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Hi, guys.

We use clock gating in our project. Our IP SC library contains only one type of clock gating cell - latch_posedge. latch_posedge.JPG

The excerpt from the project is presented here.sch.jpg
As you can see there are 2 clock domains generated from the Master Clock. I have doubts about correctness of this design.

Domain gclk_p is ok: when Master Clock's off (0) gclk_p's off (0).
But validity of domain gclk_n is in question: when Master Clock's off (0) gclk_n can be either off (0) or on (1). It depends on the value of EN port of the latch in the time of switching off (0) the Master Clock.

Am I right this design is doubtful?
I think it would be more correct to place the inverter right after the latch before registers triggered on negedge of the Master Clock.

Thanks in advance.
Andrew.
 

jducluzeau said:
Then when Master clock is off, both are off.
When Master clock is on, it depends of EN.
Click to expand...

That's right. But is it correct to do like that? Maybe dislocate the inverter of the Master Clock to ensure the certain OFF state of gclk_n?
 

if EN is not the same there is no problem to do this.
Two clock domains can be enabled at the same time.
you needn't inverter
 

So, this design is better?
sch1.jpg

P.S. We also use Internal Scan technique, so in fact the latch_posedge has the port SE (ENL = SE | EN). And TetraMAX didn't like the design with uncertain clock OFF (when Master Clock = 0) value of the registers in gclk_n domain (1'st variant of the design). That's why it turned out a problem.
 

this is not better. it is just difference.
you will have gclk_p and gclk_n dephases. It is all.
I don't understand your point.
There is no problem to have a clock domain off with tetramax. It always done for TFT for example.
 

Ok. I agree it's just different. Then let's move to another question :)

I got violation C1 caught on the domain gclk_n:

Clock Rule: C1
Clock PIs off failed to force off clock input N of scan S I (G).
Default Severity: Error

That's true. When Master Clk = 0 then gclk_n = X. So, I should just ignore that?

Thanks a lot for answers :)
 

When Master Clock =0, clk of gated cell equals 1. then the latch is transparent and gclk_n depends on EN.
During your sequence to enter in scan mode, put EN=1.
if EN=1, gclk_n =not(MAster clock), even when Master clock =0;
 

No!
Master Clock = 0 -> CLK(latch_posedge) = 1 -> latch_posedge is in HOLD state -> gclk_n = (ENt | SEt), where:
ENt - value of EN at the moment of transition of Master Clock from '1' to '0';
SEt - value of SE at the moment of transition of Master Clock from '1' to '0'.

'C1' check is perfomed by TetraMAX by switching off the clock primary inputs (i.e. Master Clock). Then both ENt and SEt are not defined (X).

---------- Post added at 00:20 ---------- Previous post was at 00:14 ----------

Maybe this tetramax requirement doesn't need to be met...
I'm a real newbie in this area. I got only 3 months experience :) That's why I have some doubts.
 

why ENt and SENt are not defined?

when you runs Tetramax, you do a sequence to put your design in scan mode.
I guess EN comes from a register. During this sequence write in this register, for example.
But in scanmode you should be able to control SEN, then control it.
If you don't,there is a problem in your design.
 
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    Rogov

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Ok. After setup_macro execution I got SE = 0; EN = X. Do you propose to write in register controlling EN?
I think it's not usual... During setup_macro it's supposed to setup JTAG controller

---------- Post added at 00:37 ---------- Previous post was at 00:36 ----------

And EN is controlled by just some internal register
 

In fact,
I thougth to control EN by JTAG register but if EN is controlled by an internal register.
Why EN=X, this register should be reseted during setup macro.
 
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    Rogov

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Ok, I think this question can be considered resolved.
Our clock gating design is ok, though it is kinda special :)

Thanks a lot! I figured it out! :-D
Great forum!
 

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