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Verilog While loop,For loop is synthesisable????

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always inside for loop verilog

For Loop is Acceptable but while loop is depend on your tool and it will not good for FPGAs
 

verilog while loop

I have to write a verilog code combining structural and behavioural statements. But i need to execute these structural code at every clock cycle. Can i write these Strustural statemnets inside the always block???? otherwise hw do i do it?? a quick reply ll be a lot of help...
 

verilog synthesis for loop

I think all loops that can be easely written out unrolled are synthesisable. For doing this, think as a preprocessor that will unroll the loop, substituting the loop variable, and there you go...
 

Re: for loop verilog

ankit12345 said:
For(i=0,i< 10,i++)
I think this works.....
where as this......
For(i=0,i<k,i++)
where k is a variable.........changes during simulation.....
I dont think it will be synthesisable........

Comments please.....
Click to expand...

One way to overcome this would be to have multiple for loops iterating at fixed values of 1,2,4,8,16..etc which are sequential in nature

if for eg you wanted to iterate the loop for k= 13 times
k = 00001101;

you can use these bits to appropriate enable a loop as in
connect k[0] to loop iterating 1 time
connect k[2] to loop iterating 4 times
connect k[3] to loop iterating 8 times
 

any loop is synthesizable if two things are taken care..
1. should be a finite loop
2. no delay statements within the loop
 

For some reason the follow Verilog code does not work correctly in Quartus II 10.0. I am trying to write a function that set all bits to the right of the most significant set bit:

Code: 
function [31:0] mask (input [31:0] tap);
	integer index;
	mask = tap;
	for (index = 1; index < 32; index = index * 2) begin
		mask = mask | (mask >> index);
	end
endfunction

The code synthesizes as if the different iterations of the for loop are concurrent.
Any explanation appreciated.

TM
 

The code you write is concurrent then the synthesis seems understanding but I don't understand what you want to do
 

What I want to do is simple. Given any input word I want to return a word with 1's in all positions right of the leftmost 1. For example, given

32b'00000001000000000000000000000000

I want

32b'00000001111111111111111111111111

Or given

32b'00010100101001010101001010010011

I want

32b'00011111111111111111111111111111

The loop should do this, since it uses a blocking assignment. Starting with

32b'00000001000000000000000000000000

after each iteration I should get

32b'00000000110000000000000000000000 // index == 1
32b'00000000111100000000000000000000 // index == 2
32b'00000000111111110000000000000000 // index == 4
32b'00000000111111111111111100000000 // index == 8
32b'00000000111111111111111111111111 // index == 16

However, in the end the code actually produces

32b'00000000110100010000000100000000

as if all iterations occur concurrantly.
 

why do you use a function and not a module?
In a module you can use an initial statement and it would be worked.
 

thanks for the reply jducluzeau, but if it doesn't work in a function, why would it work in a module? Besides there are other interconnect problems when using a module. With a function, each module that uses it can have it's own copy.
 

I never used why used function instead module. You can use module in another module.
this code should work.

module masker (mask,tap);
output [31:0] mask;
input [31:0] tap;
genvar i;
assign mask[31]=tap[31];

generate
for(i=1;i<32;i=i+1)begin:essai
assign mask[i-1]=mask|tap[i-1];
end
endgenerate
endmodule

regards
 
Thanks for the example using generate. I've never used that construct before.

I do need to figure out that's wrong with the original code, because if it's wrong I may have a problem with the project in other areas.
 

try mask = mask | (tap >> index);
I think the problem comes from this line.
Open a schematic viewer, You will see the problem.
 

I was actually going to suggest the exact opposite -- that your original code used mask = mask | (tap >> index); instead of mask = mask | (mask >> index);

even then, I don't see where you get the output you get. for example, i'd expect a pattern of 11101000100000001 as a result of a 1 being shifted 0, 1, 2, 4, 8 times. It seems to be shifting tap by 1,2,4,8 times then or-ing the result.

You might make an intermediate variable to see if this helps.
 

Personally, I wouldn't do it with for loop. Sometimes for loop helps for readability, but yours isn't very clear at a first glance. I'd rather go with case statements for a better readability unless it requires 100's of lines.
 

Re: is for loop synthesizable in verilog

For loop is synthesisable if it runs for a constant time..You can think of a hardware in which what happens if your code executes for one time, and then its replicas will be synthesized after using for loop.... Remember, anything dynamic is not synthesized..The thing is that can we visualize the scenario thats it..
 

Thanks to everyone who posted.

The correct statement is mask = mask | (mask >> index);

I dumped the result of this function out to the 7-segment LED on the dev board and verified that index*2 and index+1 actually produce the same correct results now. I'm not sure what happened to the original bug.

I decided to use a function written like jducluzeau's with a for loop, not a generate loop. This is works and is understandable.

Code: 
function [31:0] mask (input [31:0] tap);
  integer index;
  mask[31] = tap[31];
  for (index = 30; index >= 0; index = index - 1) begin
    mask[index] = tap[index] | mask[index + 1];
  end
endfunction
 

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