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Generate two non-overlapping clocks

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andrea22

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Does anyone know how it works non-overlapping clock generator?
The circuit takes a clock signal and generates a two-phase nonoverlapping clock.
The amount of the separation is set by the delay trough the NAND gate and two inverters on the NAND output.
My question is:Why these clock signal must me non-overlapped?
How each logic gate (NAND and inverters) effects that those signals are non-overlapped?
How can non-overlapping time increase?
All logic gates (INVERTERS nad NAND ) are realised in CMOS technology.
 

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Can anyone help me?
Why are three inverters needed to generate non-overlapping clocks?
 

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andrea22 said:
Can anyone help me?
Why are three inverters needed to generate non-overlapping clocks?
Click to expand...

The 3rd inverter is there for obvious reason(advice: understand the logic and you'll see why).
The 1st and 2nd inverters are there to make two clocks non-overlapping with a good separation margin(advice: consider the delay).
 
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I don't understand why are three inverters needed?
Why in the non-overlapping generator with NOR gates and inverters only two inverters are needeed?
I'm confused.Can you tell me more?
Do yo have any literature about that?
 

I don't have any literature.
Looking at the logic circuit is enough to see how it works, isn't it ?

Regarding NOR and NAND, understand the De Morgen's law and try to convert the circuit with NAND to the one with NOR by yourself. You'll see why they have different number of inverters.
 

I tried that,but I still understand why three inverters are need when I use NAND and why two inverters when I use NOR gates?
What is diffrence between NAND and NOR except in logic table?
 

If you have converted the NAND logic to NOR logic, you should have known why they need the different number of inverter as that's the result you should have come up with when you tried conversion.
There is nothing more than logic table required to understand the difference of NAND and NOR.

My final advice. DRAW THE TIMING CHART OF TWO OUTPUT OF THE CIRCUIT WITH A LITTLE BIT OF DELAY APPLIED TO EACH GATES YOU HAVE IN THE CIRCUIT. That would clarify all your questions.
 

I simulated those two circuits in PSpice.Why this feedback loop needed?
Does NAND gate and NOR gate have diffrent delay so why is diffrence in number of inverters?
Well,I need more explanation,I'm really confused.
 

THe circuit is extremely simple. If you don't understand that circuit,including the difference with NOR and NAND, you should study the basics of digital design one more time. Read a digital design book.
 
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I know the diffrence between NAND and NOR if you mean on logic table.
But dont understand why are three inverters needed?
Can you explain me how this circuits works,please?
What I ment is how each logic gate in this
circuits effects on non-overlapping time?
Because when I simulated this circuit in Pspice after 1 inverters clocks are non-overlapped (non-overlapping time is very small),after two inverters clock are overlapped,and after three inverters clock are non-overlapped.
As you can see in this circuit two inverters are enough to generate non-overlapping clocks.
Thank you.
 

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  • With NOR.bmp
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Andrea,
a nor b = not(a) and (not b)
then
not(a nor b)= not(a)) nand not(b)

then there is one more or less inverters to nand-based circuit than not-based circuit.

Regards
 
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