tandt_53
Newbie level 3
can u help me? I have a problem with digital design as following:
"build a 8 bit up/down counter with I/O: clk, set, reset, data_in, data_out.
use VHDL language, build the testbench to emulate and verify this counter."
thanks alot!
"build a 8 bit up/down counter with I/O: clk, set, reset, data_in, data_out.
use VHDL language, build the testbench to emulate and verify this counter."
thanks alot!