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yes for biasing thats what would make sense..but i dont know whats the right way to choose device size given a choice of both w and l for cmos? any book that desribes this well.
You would usually go with picking the smallest width for the NMOS that the technology allows or a typical transistor is characterized at. Then you make the PMOS 2-3 times wider to account for the difference in mobilities. This would be a unity gate. After that you scale these dimensions up according to the load you have to drive from each gate. Googling for Logical Effort will give you more information on how you could do that systematically.
If its unity, the CMOS device would be symmetrical which gives the advantages of full voltage swing as well as low power consumption. But, on the other hand, the transistors required is more compared to fully NMOS implementation
Yes, NMOS should always be minimum length constrained by the fabrication technology. Since the difference in mobility of electrons and holes, PMOS has to be 2 to 3 times NMOS.
Is there any situation when you consider different lengths for nmos and pmos? Is there any situation when you would like to go away from minimum length?
PMOS length is always 2 to 3 times NMOS. Why would you want to go away with minimum length? Minimum length will make your device smaller as long as we have the technology to do them.
Thats what I want to know, if i have voltage to operate can i choose larger length so that Vt variation is less over process, or Ro is larger, or anything else? does minimum channel length give me advantage then?
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