Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

need help regarding interfacing ADC 0808 with XILINX spartan 3E FPGA

Status
Not open for further replies.
L

longbeach2

Newbie level 1
Newbie level 1
Joined
Sep 21, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,289
Hello guys,
I am trying to interface ADC 0808 with spartan 3E FPGA.can anyone please tell me how to do verilog program of this?.ADC 0808 works at 450 KHz and fpga 50 Mhz.Do i have to use different ADC or i can do it with 0808.
please help.
thank you for your time and help
 

how do we divide the clock frequency ?? it would be better if you give me a link with the verilog code in it.... plz do help as soon as possible.... its urgent.
Jack// ani said:
You can you ADC0808, however you have to divide 50Mhz clock down to something which 0808 can handle.
Click to expand...
 

You may use external clocks if the option is available.
 

use a clk divider as follow:
Code Verilog - [expand]
1
2
3
4
5
6

reg     [10:0] clk_divider=0;
    wire        fs;
    assign       fs = clk_divider[4]; //    fs = GlobalClk/5
 
    always @(posedge GlobalClk)
        clk_divider<=clk_divider+1;
 
Last edited by a moderator:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top