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on board adc interface

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techtronz

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Sir, i am working on adc interface..... i am using a bitmapper virtex II pro board which has a onboard adc (ad9240).... can anyone suggest me how to go about writing the vhdl code for it..... the parameters to be considered and what my port list should contain.....

Regards.

techtronz
 

Very simple, Read the Data sheet, and use Example designs came with board.

It has been a continuous approach from vendors to provide codes for each component interfacing that are available on Board!
 
Sir, had example designs been there it would have been easy..... but the board is 10 years old....... and example designs are not there..... The adc specifications are
input range - 0 to 5v
sampling rate - 10 msps
resolution - 14 bit
it has control input
1.out of range (otr)
2.adc clk

So, how much should the frequency of adc_clk be.......
and since its a onboard adc........ if we provide an analog input through a connector.... will the adc itself start the conversion or am i supposed to use the signals start of conversion and end of conversion........ Do post if there is any example code for an onboard adc......
 

are you aware that you know the model of the ADC in question?
perhaps you also have a schematic of the board.

In anycase, I agree -- look at the datasheet and schematic. We have no idea where the ADC gets its clock, or where/if the FPGA gets a copy of this clock from. perhaps the ADC provides the clock (poor design for IF sampling).

As for sampling rate, that is usually determined by the application, as well as the on PCB hardware used for clock generation.

edit - perhaps the FPGA provides the clock. That's what would be bad for IF sampling.
 
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    techtronz

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thank you for your time....... the adc gets the clock from the fpga......... i have attached the datasheet of adc that i am using....... can u just go through it and suggest the needfull.....
 

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  • AD9240.pdf
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I charge for this kind of work by the hour. How much are you willing to pay me to do your work?
 

Hahaha! love the "I charge for this kind of work by the hour" ..

Anyhow, after a super quick look at the datasheet, seems like the Figure 1 is telling you to send out a clock to the beast. In return, it gives you data.
And, also, Switching Specs give. Tc = 100 ns. Drive the chip with a clock of at least this period (ie 10Mhz clock). In your VHDL, use a clock at twice this speed.
Then @20Mhz,
. 1st rising egde, ADC clock goes high
. 2nd rising edge, grab data and OTR present on line
. start again
Reading the datasheet, i saw something about the Rbias beeing the frequency selector or something... take this into account (oh, and Shannon or Nyquist) for sampling frequency.

Ciao for now
 
the FPGA is driving the clock. In this case, you have the sample clock. I would simply pass the clock out (use an ODDR component with D1=0, D2=1) and use the rising edge of the same clock to clock data in (ensure a IFF is inferred in the _pad.txt report). It looks like either clock polarity will work though. The clk to out for the ADC is 8-19ns. so clocking data in on the same edge will still meet setup/hold times for the input. clocking on the opposite edge should meet setup/hold as well.
 
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