vipinlal
Full Member level 6
I know VHDL and would like to learn a hardware verification language.I googled and found that these are the common languages used right now: SystemVerilog, OpenVera, e, and SystemC.
So right now I am confused about learning which one among the ones listed above.I searched here and found this link:
https://www.edaboard.com/threads/34629/
But this was 5 years before and the situation may have changed a lot by now.
My question is which verification language is most used in the industry to test the HDL design in the functional level?
I hope that all HVL's are capable of testing the design even if the design is made in VHDL or in Verilog.
Please guide me...
So right now I am confused about learning which one among the ones listed above.I searched here and found this link:
https://www.edaboard.com/threads/34629/
But this was 5 years before and the situation may have changed a lot by now.
My question is which verification language is most used in the industry to test the HDL design in the functional level?
I hope that all HVL's are capable of testing the design even if the design is made in VHDL or in Verilog.
Please guide me...