How to code onchip power supply module in Verilog?

Hello all,

I'm designing a chip. It has a on-chip power supply and it feeds all the powers on the die. (So all the digital blocks rely on it.)

I finished the analog design and I want merge it with my digital logcis.

Since I want to use Encounter for full chip layout and clock tree synthesis, I'm planning to generate LEF and Verilog file for that power supply circuit.

I can do the LEF generation part, but I don't know how to code the verilog file for it.

Does anybody know how I can acheive this?

Thanks,

Newmedia

You need to instantiate this sub-component in the digital top.
This module can have some input/output, to control the voltage, ..., this pin are also require inside the liberty file, and in the LEF file you must add the power pin where you will connect the power ring/strap that supply the digital (std cell memories, pad....).

during the synthesis, the tool will map the component to the liberty file
during the floorplan, the tools will use the LEF extract model, to place this one (manually or automaticly), you will define the power to be connected to this module to the std cell...
And the CTS-hold time-routing will be done as usual, without any impact due to this module.

It is the same if you supply the design through the pad, but in this case, the pad are replace (or be added) with this analog component.

Hello rca,

Thank you for replying.

So... what you are saying is this. If I'm wrong, please correct me.


Let's say I have a power supply circuit schematic, and it uses VDDIO and VSSIO (higher voltage than digital core) and generates VDD.

I'm using DC, so I don't need a liberty file. Instead, I will write a non-synthesizable rosc RTL.



module onchip_power (vddio, vssio, vdd);
input vddio;
input vssio;
output vdd;
endmodule


Other designer will implement the circuit in full custom flow. (Let's assume the designer did not finish the design. So there is no LEF)

After RTL simulations of my whole circuit, I will synthesize the other blocks.

Then, I will use Encounter to start Place & Route. I know there is an option which can define macro block size without an LEF file in Encounter.

I think until here is clear. However, I don't know how I can do this.

"you will define the power to be connected to this module to the std cell..."

Can you elaborate this line for me?

Thank you,

Newmedia

1- you need to have the module included in the netlist to be able to place the module during the floorplan phase.
2- during the floorplan phase, in encounter for example, you use the following command
globalNetConnect vdd -type pgpin -pin VDD -inst * -module {} => you add a connection between each power pins VDD, of all std cell & macro..., to the net vdd.
by the same command you will also connected the vddio / vssio to pads for example. In case your module include the vddio/vssio pad, you can only declare a INOUT VDD. Depending how you made the final LVS, the vddio/vssio need to be declare or not, but this is a other discution .
after you add a real net via addRing/addStripe/sroute to connect the power pins together.
Then in your LEF the output VDD (direction is less important in LEF file, direction INOUT is more relevant for a power pin) require to be declare as "USE POWER" (USE GROUND for vssio for example)
that's fine ?

Hello rca,

Thank you so much. a kudos for you. Now I understand what you are saying.

Do you mind if I ask one more question?

I want to do Verilog simulation with PADs and synthesized gates.

However, my PADS module look like this.


#INPUT BUFFER
module I1025(PADIO,VSS,VDDIO,VDD,R_EN,VSSIO,DOUT);

input PADIO;
inout VSS;
inout VDDIO;
inout VDD;
input R_EN;
inout VSSIO;
output DOUT;

RECEIVER RECEIVER (
.pad ( PADIO ),
.EN ( R_EN ),
.DOUT ( DOUT ),
.VDD ( VDD ),
.VSS ( VSS ),
.VDDIO ( VDDIO ),
.VSSIO ( VSSIO )
);

endmodule


And my logic gate look like this.

#AND GATE
module AND2X1 (IN1,IN2,Q);

output Q;
input IN1,IN2;

and #1 (Q,IN2,IN1);

`ifdef functional
`else
specify
specparam in1_lh_q_lh=52,in1_hl_q_hl=50,in2_lh_q_lh=59,in2_hl_q_hl=56;
( IN1 +=> Q) = (in1_lh_q_lh,in1_hl_q_hl);
( IN2 +=> Q) = (in2_lh_q_lh,in2_hl_q_hl);
endspecify
`endif

endmodule


As you can see there are VSS,VDDIO,VDD,VSSIO. If I want to do Verilog/Primetime simulation, how do i have write the top module?

My guess is this.

module core_with_pad (VSS,VDDIO,VDD,VSSIO, ... );
inout VSS;
inout VDDIO;
inout VDD;
inout VSSIO;

supply0 VSS;
supply1 VDDIO;

I1025 U1(.VDD(VDD),.....);

endmodule


Do you think this is reasonable approach? Please give me some hints.

Regards,

Newmedia

The place & route tool will generate the latest netlist. You may have two netlists, one including the power net used for LVS (with Calibre for example), and a second without any power information.
Then, with this second netlist, you will do your STA and generate the SDF (SDF could also generate with the P&R tool).
And you can simulate your second netlist backannotated with the SDF.
My question is: why do you need to simulate the netlist with SDF? Do you used LEC?
Or I miss something?

rca said:

The place & route tool will generate the latest netlist. You may have two netlists, one including the power net used for LVS (with Calibre for example), and a second without any power information.
Then, with this second netlist, you will do your STA and generate the SDF (SDF could also generate with the P&R tool).
And you can simulate your second netlist backannotated with the SDF.

Click to expand...

Does the latest netlist mean the netlist with power supply nets? Yes. I agree that that netlist can be used for LVS. However, the pad module described in my previous post, it has power nets. How the Verilog module with power (e.g. PADS) and without power (std cells) can be simulated at the same time? Are you saying the P&R tool (encounter) will strip out the power nets from the pad? I guess this question is due to lack of my knowledge. Please help me out. I can not understand how I can simulate PADs and STD cells at the same time in a Verilog simulator. ????

rca said:

My question is: why do you need to simulate the netlist with SDF? Do you used LEC?
Or I miss something?

Click to expand...

If the netlist means the netlist with power nets, my answer will be "to check the impact of the different pad selection". Let's say I read the PAD library documentation thoroughly, and I understood what will be the proper I/O cell for specific pins. Even tough I'm sure, I have to verify it, right?

This leaves a big questions: How I can simulate PADs with power net and STD cells w/o power nets at the same time

Thank you so much rca. I appreciate your help.

When you do a simulation verilog + sdf, you do not include the power notion. Then you need to have model without power, for example power pad don't have any behavioral description in the pad io verilog library model, but the input/output/bidirectional pads have model and should not contain any power pins (like the AND gate).

Who provides the PAD model you describe before? You may remove this power information to use this pad, but power pad are not require for the post simulation.

The post simulation does not include any power information.

Till now we discuss about a design without UPF or CPF definition, that's right? This constraints are onyl requires for advanced power functionnalities not for standard power pad connections.

Hello rca,

I really appreciate your help. I found someting, and I want share with you and other members.

rca said:

When you do a simulation verilog + sdf, you do not include the power notion. Then you need to have model without power, for example power pad don't have any behavioral description in the pad io verilog library model, but the input/output/bidirectional pads have model and should not contain any power pins (like the AND gate).

Click to expand...

Now, I realized what gave me all this confusion. I'm using Synopsys 90nm educational libarary. In the library, there are several I/O's with power pin definition. Now I'm pretty sure the purpose of the power pins. The pins are used to model undefined output.

Let's look at this.


wire power_valid = ( VDD == 1'b1 ) && ( VSS == 1'b0 ) && ( VDDIO == 1'b1 ) && ( VS

always @( power_valid or pad or EN )
begin
if ( !power_valid || ( pad === 1'bx ) || ( EN === 1'bx ) || ( EN === 1'bz
DOUT = 1'bx;
else
if (EN && pad === 1'bz)
DOUT = 1'bx;
else
DOUT = pad;
if (!EN)
DOUT = 1'b0;
end

As you can see the code check supplies are connected to proper logic level. And if not, it generates "X". I think this is done for checking purposes.

To prepare pad information for Encounter, I will code the pads like this.

module top (x,x,x,x,x,);
AVDD AVDD (.VDD(VDD),....)
DUT DUT(.....);
end module

Since the pads does not have connection to power supply nets. I will use globalNetConnect.

rca said:

Who provides the PAD model you describe before? You may remove this power information to use this pad, but power pad are not require for the post simulation.

Click to expand...

I have IBM45nm SOI, and Synopsys 90nm Educational library. They are the same.

rca said:

The post simulation does not include any power information.

Till now we discuss about a design without UPF or CPF definition, that's right? This constraints are onyl requires for advanced power functionnalities not for standard power pad connections.

Click to expand...

No. We are not discussing UPF or CPF.

I guess I cleared my doubts.

Thank you so much rca!