cie40
Junior Member level 1
Hi,
In Verilog, I'd like to set the address 0 of the memory array below to 8'hFF.
[ memory model ]
reg [7:0] MemoryBlock [0:EEP_END_ADDR];
[ testbench ]
force tb.u_memory_model.MemoryBlock[0] = 8'hFF;
But I had an errror.
'Illegal use of a bit-select, part-select, member-select or mda element'
Let me know a good way...
Thanks.
In Verilog, I'd like to set the address 0 of the memory array below to 8'hFF.
[ memory model ]
reg [7:0] MemoryBlock [0:EEP_END_ADDR];
[ testbench ]
force tb.u_memory_model.MemoryBlock[0] = 8'hFF;
But I had an errror.
'Illegal use of a bit-select, part-select, member-select or mda element'
Let me know a good way...
Thanks.