cyboman
Member level 4
i'm reading a book on verification with system verilog. the book contains sample code which i have questions about
here is the code:
arbif.request[0] is of type logic. the same goes for arbif.grant[0]
question 1
i always used and was taught to use always @(posedge/negedge ) only with clk or reset. i was told the simulator and the synthesizer will not be able to understand it. so why are we using it here?
question 2
i have never seen posedge statement in another posedge. what would happen here? will the simulator simply ignore all the positive edges of arbif.request[0] when it sees arbif.grant[0]? will it simply wait for a posedge on the arbif.grant[0] and then continue execution?
any help is appreciated.
here is the code:
Code:
always @(posedge arbif.request[0]) begin
$display('displays something');
@(posedge arbif.grant[0]);
$display('another something');
endarbif.request[0] is of type logic. the same goes for arbif.grant[0]
question 1
i always used and was taught to use always @(posedge/negedge ) only with clk or reset. i was told the simulator and the synthesizer will not be able to understand it. so why are we using it here?
question 2
i have never seen posedge statement in another posedge. what would happen here? will the simulator simply ignore all the positive edges of arbif.request[0] when it sees arbif.grant[0]? will it simply wait for a posedge on the arbif.grant[0] and then continue execution?
any help is appreciated.
