DDR2 Signal Integrity Simulation & Timing Budget calcula

ddr2 signal integrity

Hi Everybody...

Recently I have simulated a DDR2 266 MHz/533 Mbps memory interfaced with Power QUICC processor to analysis following Results that affect signal quality at the receiver for SSTL 18 signaling…

Proper selection of termination value (ODT)
Data Valid Window & Timing margins (Eye Width & Eye High)
Timing Budget calculations (read & write cycle)
Slew Rate
Over-shoot & Under Shoot
Cross talk analysis

If you have any doubt related to DDR2 Memory Interfaces I may help you….

signal integrity simulation

hi,
I am using allegro 15.7 gxl for my design , and I have simulated the DDR2 data and address bus , but the point is , I can't understand/infer any logic from the simulation graph being generated.
Could you plz guide me through step by step method so that I can infer any conclusion wether the design would really work on the predefined criteria(266 Mhz).

Also I would like to know how do you set the values for the constraints ex. relative propagation delays, for signal integrity, timing, and for routing in the ECsets(allegro).

That would really help me in my design,
I would be highly obliged ..
Thanks and regards
Niraj

ddr2 timing

Hi
CAn u explain about Timing Budget calculations (read & write cycle).

ddr2 si simulation

Hi Niraj,
Bidirectional data bus signal like DQ & DQS and more import for than address bus except loading condition for address line.
The best way to find the quality of signal is to analyze eye-diagram at receiver. Since DDR2 memory works on SSTL 18 signaling you have to fist understand SSTL. For SSTL refer Stub Series Terminated Logic for 1.8 V (SSTL 18) by JEDEC “JESD8-15a.pdf” (free Doc).
This doc you find the Single-Ended Input Signal Levels & Differential Input Logic Levels for high1 & low logic0 respect to ref Voltage.
From eye diagram you need to find eye-opening, slew rate derating & eye high at different ODT setting for correct logic.
I have used Mentor Graphics Hyperlynx 7.7. I don’t have any idea of cadence SI software. But both will be same one way or other.
If you want more detail please fell free to write me.

AMIT

Added after 25 minutes:

Hi Venkat

The top level timing budget include three component
•Transmission Skew
•Receiver skew
•Board Skew Budget

The transmitter and receiver skews can be obtained from the device data sheet. It is then split up for the setup and hold portions.

The Board skew budget is most important for DDR2 interface and you must simulate the design to find following
•ISI (DQ & DQS)
•Crosstalk (DQ & DQS)
•VREF noise
•Path length mismatch
•CIN mismatch

For more information you can refer the DDR2 memory vendor data sheet.

Amit

ddr2 simulation

Is there any length matching requirement for clock and DQS?

timing budget ddr2

can u tell me about the schemes of DDR2 terminations?

ddr timing budget

sandhya.im said:

can u tell me about the schemes of DDR2 terminations?

Click to expand...

chk this for DDR2 Termiantions

https://download.micron.com/pdf/technotes/ddr2/TN4720.pdf

allegro ddr2 simulation

Hello Amit,

Can you please send me how to interface IC's, what points are checked in datasheets especially for Memories like DDR2 and Flash devices.

(Like calculation of Setup and Hold Time).

During SI, from IBIS model can we get all these parameters and verify our theortical calculations.

i wanted more information on DDR2 SI simulation? Can you please let me know.

regards
ragh

ddr 2 read timing budget

Hi there,
I am using PCB SI Allegro for DDR2 simulations. So far, I added all of the constraints for min/max and relative propagation delays in the constraint manager according to the datasheets and ap-notes. I also wrote a PCB placement&routing instruction for layout section. I also built the associated IBIS models and am waiting to get partially DDR2 routing to simulate and this is my first time. what should I do when I get the routed DDR2? run simulations for DQ, DQS and other signals? how can I see the skew between DQ and DQS or with CLK+/-
Thanks,
Semi

ddr signal integrity ibis

Hello ,

Which tool are you using for Simulation?
What is the backend interface (i mean to say Processor used for DDR2 interface).


regards
raghu

ddr2 timing explained

I am using Allegro PCB SI tool. The DDR2 got connected to Virtex-5.
Semi

Re: ddr2 signal integrity

aps2itm said:

Hi Everybody...

Recently I have simulated a DDR2 266 MHz/533 Mbps memory interfaced with Power QUICC processor to analysis following Results that affect signal quality at the receiver for SSTL 18 signaling�

Proper selection of termination value (ODT)
Data Valid Window & Timing margins (Eye Width & Eye High)
Timing Budget calculations (read & write cycle)
Slew Rate
Over-shoot & Under Shoot
Cross talk analysis

If you have any doubt related to DDR2 Memory Interfaces I may help you�.

Click to expand...

Hi,

Me to using freescale Power QUICC processor( MPC8377e ) and interfacing it with 8 DDR2 SDRAM modules each of 1giga bit (64mX16) hynix DDR2 SDRAM, my doubts are:-
1) I am not using ECC pins of processor so shall i leave them floating i.e. NC as datasheet of processor only says that these are required to be GNDed in case of DDR1 and nothing about DDR2..
2) What about unused chip selects, unused MODT pins of processor as i am using cs0 for 4 DDR2 modules and cs1 for rest of four DDR2 modules. as these are o/p pins can i leave them flaoting.
3) Though ram has ODT functionality but still i have used 22ohm resistance on all DQS, DM,DQ signals. for testing purpose ...........does this affect my ckt??


I will highly acknowledge and appreciate Any valuable feedback,help, documents, links .
Thanks

Re: DDR2 Signal Integrity Simulation & Timing Budget cal

Hi,

1. ECC Pins can be pulled high to 1.8V
2. I just left unconnected the Chipselect pins in my design, i didnot face any problem while testing
3. When already you have ODT - what is purpose of having series termination.
I feel after your simulation results you can remove those.

Have you seen the freescale application note on DDR2
**broken link removed**


Regards
Raghu

Re: DDR2 Signal Integrity Simulation & Timing Budget cal

Dear All,

There is no need of any termination on the board for the data/mask/strobe signals in ddr2. We have 3 alternate ODT values in the memory chip i.e 50/75/150 ohm which can be controlled using ODT pin from processor.

Similarly in the freescale processor ODT terminations are available for the data groups. Adding a termination in the board is not at all required and also it adds to BOM.


Regards
Siva

Re: DDR2 Signal Integrity Simulation & Timing Budget cal

There is a lot of good information on designing and simulating the DDR2 memory bus in the Altera/Micron/Cadence DDR2 Design-in IP Portfolio ... https://www.cadence.com/rl/Resources/downloads/Micron_Altera_ddr2kit.zip

Re: DDR2 Signal Integrity Simulation & Timing Budget cal

Thanks for your suggestions.

Hi, I have few clarifications in the frequency of operations?
1. "suppose am using DDR667 MBPS, at which frequency I have to simulate my data, DQS, CLK and ADDRESS lines"?
2. I was told that the address lines will function only in half the speed of clock is it true and what is the reason? Kindly correct me..
I am Using Hyperlynx 8.0 version tool

Hi,

DDR667Mbps is a data rate. U have to simulate DDR signals in the below frequency.

1) Data - 667Mhz

2) CLk - 333.5Mhz

For the address lines u need to check whether 1T or 2T clocking scheme is adapted. If 1T clocking scheme is used you need to simulate the Address/Command/Control signals as 333.5Mhz same as clock.

In some cases due to heavy loading of memories, slew rate of the address signals will be very low. in that case you have to adopt 2T clocking scheme- means the address/command signals will be valid for two clock cycles. In 2T clocking the address/command frequency will reduce to half of the clock frequency i.e 166Mhz in our case.

Note: Control signals are always 1T(in our case 333Mhz) clocking scheme irrespective of the address/command frequency.

Hi,
Anyone here working with Hyperlynx? I got few clarifications about the crosstalk analysis on both batch simulation and Line simulation.
1. The crosstalk considered is for Layer to layer or adjacent nets?
2. Can we do crosstalk analysis in Line sim say for Pre-Si analysis. If so how to interpret from the waveforms it generates.

Kindly clarify

---------- Post added at 18:14 ---------- Previous post was at 18:11 ----------

Regarding address Clocking 1T or 2T how can we find that out. Does that depend on the application or perspective of layout person.?

Hi,

We cannot run a cross talk analysis in LINESIM. we need to run. There is only one way to get the crosstalk analysis report in hyperlynx is by running the batch simulation report. It just provides only one report for relection, crosstalk all.

Regards
Shiva.

---------- Post added at 09:24 ---------- Previous post was at 09:23 ----------

techzee said:

Hi,
Anyone here working with Hyperlynx? I got few clarifications about the crosstalk analysis on both batch simulation and Line simulation.
1. The crosstalk considered is for Layer to layer or adjacent nets?
2. Can we do crosstalk analysis in Line sim say for Pre-Si analysis. If so how to interpret from the waveforms it generates.

Kindly clarify

---------- Post added at 18:14 ---------- Previous post was at 18:11 ----------

Regarding address Clocking 1T or 2T how can we find that out. Does that depend on the application or perspective of layout person.?

Click to expand...

1T and 2T is for address/command signals only and the same is dependent on the loading of the DIMM modules.