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Is wait statement syntehsizable in VHDL?

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kalaiyarasan

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In VHDL whether wait statement is synthesizable or not...
if it is partially synthesizable in which kind of statement it is synthesisable
 

wait statement

In VHDL, wait statement is not synthesis able at all.The maximum you can do is create a counter and wait for the count value till it reaches a preset value.

--vipin
https://vhdlguru.blogspot.com/
 
Re: wait statement

If you use it as a 'process', it's synthesizable.
For eq : wait until clk'event and clk = '1'...
 
wait statement

the following template for processes is also synthesisable:

Code: 
process
begin
  wait until rising_edge(clk);
  .....
end process;
 

Re: wait statement

It is not recommended coding practice to use wait statement for synthesis. use 'event attribute, that too for clock rising edge.

If you want to create a delay, then go for counter implementation with enable.
 
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