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How to Layout Deep Nwell in TSMC 0.18um HV technology

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VASANSNS

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deep nwell layout

Hi all,
I have tried to layout the Deep Nwell using the library TSMC 0.18µm tech (in cadence as well as magic) , but i do not see that layer defined at all.I searched for online documentation and it said that deep nwell was optional. How do i get this layer?

Also Is this layer same as NBL?

Regards
VSNS
 

deep nwell

Hi,

Yes, NBL is used for bipolar process, DNW is used for CMOS process but both will serve as nosie isolation layer for NPN and NMOS correspondigly.

NBL- N+ burried layer
DNW- Deep NWELL

thanks
Vinoth
 

how tsmc 0.18 npn

Exactly right.
Could you send me the TSMC's PDK? 0.18um rf or 90nm.
 
Re: how tsmc 0.18 npn

Mr.dal said:
Exactly right.
Could you send me the TSMC's PDK? 0.18um rf or 90nm.
Click to expand...

PDK is usually confidential and could not be spreaded out casually.
 
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