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Can be done by a PLL, either analog (e.g. CD4046) or an "all digital" PLL (DPLL respectively ADPLL) logic design.
The latter could be modelled in Verilog.
If you can't afford PLL and your design is not sensitive to duty cycle variations, then you may want to consider a 2-input XOR. Put a delay buffer on one of the inputs and then tie the two inputs together. This gives you clock time two. Chain as many of them together as necessary to get higher multiplications. At the very last stage you can register the output to even out the duty cycle. Also, you may have to manually adjust the buffer delay to 1/2 of your clock period during layout.
Note that this does not give you odd multipliers. For that you need to use counters to count both edges...
Search all digital PLL in google. U can get the required documents
u have to use two divide by N counters.
have to design divide by N counters. Nothing complicated more than that
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