Jugantor
Junior Member level 2
Hi All,
I am trying to perform gate level fault simulation using verilog by simulating faults at the output of internal gates randomly. Say for example, outputs of gate A & B go to inputs of gate C. Now I want to simulate a fault in C by inverting the output of C for 1 simulation cycle and reverting it back in the next. This can be done using the force and release commands.
My question is how do I automate this step ? like how do I randomly select the outputs of my gates of the DUT from my testbench, without explicitly having to mention what gate to select ?
Right now, as you can see in the code below, I am explicitly saying which gate to select based on the value of sel. This step gets cumbersome when the number of gates is huge (in this case 35)
Any kind of help is highly appreciated.
Thanks!
I am trying to perform gate level fault simulation using verilog by simulating faults at the output of internal gates randomly. Say for example, outputs of gate A & B go to inputs of gate C. Now I want to simulate a fault in C by inverting the output of C for 1 simulation cycle and reverting it back in the next. This can be done using the force and release commands.
My question is how do I automate this step ? like how do I randomly select the outputs of my gates of the DUT from my testbench, without explicitly having to mention what gate to select ?
Right now, as you can see in the code below, I am explicitly saying which gate to select based on the value of sel. This step gets cumbersome when the number of gates is huge (in this case 35)
Code:
sel = {$random} % 35;
if (sel == 6'd0)
begin
#1 force a0.n12 = !a0.n12;
#1 $fdisplay (desc3, "Error at gate #%d | %d | %b",sel, col_in, xtraOut, cout, z1[3], z1[2], z1[1], z1[0], z2[3], z2[2], z2[1], z2[0]);
#1 release a0.n12;
end
else if (sel == 6'd1 )
begin
//node2
#1 force a0.n14 = !a0.n14;
#1 $fdisplay (desc3, "Error at gate #%d | %d | %b",sel, col_in, xtraOut, cout, z1[3], z1[2], z1[1], z1[0], z2[3], z2[2], z2[1], z2[0]);
#1 release a0.n14;
end
else if (sel == 6'd2)
begin
//node3
#1 force a0.n15 = !a0.n15;
#1 $fdisplay (desc3, "Error at gate #%d | %d | %b",sel, col_in, xtraOut, cout, z1[3], z1[2], z1[1], z1[0], z2[3], z2[2], z2[1], z2[0]);
#1 release a0.n15;
end
Any kind of help is highly appreciated.
Thanks!