Designing DDC(digital down converter)

hello every one,
i am new in vhdl, i have to design DDC(digital down converter), in which we process RF frequency, i mean to say we have a rf front end daughter board,which convert rf into IF(intermediate frequency).then this signal passes from ADC and from ADC we get digital output we need to process these digital output via DDC,
so any one please suggest me from where i start,or suggest me some place where i found some VHDL DDC codes.
Thank you in advance

Hi,
It is a fundamental thing of communications engineering. You need to read a book on basics of digital communications. And another thing is that each down converter is custom made for particular frequency requirement. So source codes from others work may not help you on first hand. If not sure about designing then buy IP or better to learn and build your system.

Anyway, take output from ADC and multiply it with the output from local oscillator (DDS/NCO) and put low pass filter of required bandwidth after the output of that multiplier. You will get your Down-converted output.

For your information, when that RF input was converted into IF, that process was also down conversion. Perhaps you should look into that for the fundamental.

Hi sir,
Thanks for replying,i am final year engineering student, and i have to submit my final project within one month,i have to design 256 channel DDC with Rf front end, i just complete my Rf front end part and get stucked in DDC, i buy Xilinx Virtex 5 FPGA and install ISC_DS tool simulator, i successfully run few my self made VHDL program,i have theoretical knowledge of my project but to implement it and for practical i am so worried and due to time constrain i am soo confused that how to write VHDL codes for starting DDC and how to write codes for CIC and FIR filter, i am getting Rf to IF signals and digital samples from ADC with rate of 110 mega samples/sec , Rf frequency range is 860-1Ghz,processing speed of DDC will be 110 Mhz, so this is a brief explanation of what i have to do, and because of shortage of time i was asking for some help and some place where i could get codes.
Waiting for your reply.
Thank you in advance

Hi,
One month as a beginner is extremely difficult to implement this task.

1. Do one thing, instead of writing your VHDL code, use IP cores readily available in Xilinx ISE. You can find cores for FIR, CIC, DDS/NCO/DCO.

2. RF frequency does not matter now. You transferred it to IF. Tell me IF frequency range.

3. Are you planning for ADC undersampling?

4. Are you planning for Digital PLL / Costas Loop with feedback at Down-conversion or it is just a straight forward down conversion?

5. What is the output frequency of the NCO in down-conversion? Are you converting the signals to Zero-IF or some another IF frequency?

6. All 256 Channels can not be converted to Zero-IF (baseband) at the same time. They have different carrier frequencies, right? You will have tune your NCO for each channel whenever you need it at baseband. There is a provision in NCO IP Core to select center frequency by choosing different variables. You need to look into the documentation of that.

Since you know the theory, it should be easy to implement. It is the same logic as in Analogue (RF to IF) but with Fixed data type. Careful with NCO frequency selection and CIC/FIR bandwidth.

I hope it helps.

Hi sir,
Sorry for replying late, my RF front end got some problem,so was busy in rectifying that problem.
1. As you told me that instead of writing your VHDL code, use IP cores readily available in Xilinx ISE, for my general program i use ieee.std_logic_1164.all library, but i am unable to understand how to call these IP cores which u are talking about, sorry for that.
2. IF frequency range is near about 70 Mhz.
3. Sir i am unable to understand this point :- Are you planning for ADC undersampling? How could i come to know ADC oversampling,undersampling.
4. There is no loop back,its straight forward down conversion.
5. Yes i am converting the signals to Zero-IF.
6. sir i just break 256 channels into 64+64+64+64,i am trying to make 4 ddc each have 64 channels,its my idea what i have in my mind,if you suggest me something better your most welcome and i am already using NCO for channel selection as u told .
waiting for your reply
Thank you in advance.

nytman, xilinx has something called "coregen", which is a similar concept as closed source binaries. They give you access to complex functions, but generally not the code used. Often, the output is a "netlist", which can be added to the project. Xilinx has some cores for CIC, FIR, and DDC applications.

#3, if you have a 70MHz IF, then base-band sampling would sample at 140MSPS. slightly more if there is a signal with some bandwidth.

at the same time, sampling at 110MSPS would cause 70M to alias back to 40MHz (4fs/11). If you can change sampling rate, you can move this toward fs/4. you might find that a lower rate is a better choice.

#6, FFTs are often employed for channelized systems. There are several systems-leve issues, and implementation issues to consider. really, its probably better to remove this requirement from the first attempt.

Hi sir,
thanks for your precious suggestion,i tried as you told and i got CIC compiler in IP Core, but i didn't get anything related to DDC application,i got only 2 libraries one for CIC and another is for FIR,and one more thing i would like to tell you that we are using webpack license ISC_DS,is there any limit on IP Core libraries in that pack ?
Waiting for your reply.
Thank you in advance.

Hi

1. IEEE.std_logic_1164 is general purpose library for all VHDL code. In ISE installation, you can find a programme called "Xilinx Core Generator". It generates IPs. You can configure many parameters for any components. NCO, Multipliers, FIRs are available. Once you finish with the configurations, you can generate the core and it will produce .edn and .vhd files. You need to include that .vhd file into your code as a component. You can get better understanding with some demos from ISE

2. You have to be precise with IF frequency range. Last time you said you want to sample your ADC at 110 MHz but now you say your IF is about 70 MHz, it does not make sense. Either choose higher sampling ratio or go for ADC undersampling. What is the total range of IF signal.

3. ADC undersampling means you can sample your analogue signals below nyquist sampling frequency. It will produce aliasing products and you capture that aliased product instead of original signal.

4. fine

5. fine. You have 256 channels, means 256 carrier frequencies. You need to tune your NCO for each carrier frequency to convert the signal at zero-IF

6. 256 to 64*4 is fine but your design will be increased four times. You will have to place NCO, CIC and FIR four times. The only benefit is that your will get 4 parallel output channels. If you do not have such requirement, go for single DDC, it will save your FPGA area.

DO THESE:
1. Make a table for all 256 channels and their corresponding IF frequencies (carrier frequencies).
2. If you choose ADC undersampling then carrier frequencies of your channels will be changed. In that case repeat first step with new carrier frequencies.
3. These carrier frequencies will determine the necessary phase increment values of your NCO. Make a table for each phase increment values corresponding to its carrier freqencies.
4. Select 3rd order CIC and very narrow band LP FIR. If you are using CIC for downsampling then there will be multi-clock domain between CIC output and FIR input. Take care of that issue very well.

Added after 2 minutes:

If I am correct, with webpack license you can run paid IP cores for only one month after downloading into FPGA.

Added after 1 minutes:

Check www.opencore.org

You will get all your IP free of cost and they are technology independent also.

Hi sir,
Thanks for suggesting me, sir i tried as you told, sir in my ISE 12.1 i am unable to found DDC libraries,i get DUC libraries but no DDC library,so that's why in the same time i parallel start designing the same DDC in matlab, we are facing problem in designing channelizer and i get some demo code for GSM for 4 channel design in which i am getting one simulation error:

Failed to find library 'xbsIndex_r4' referenced by 'gsm_ddc_cic/ System Generator1'. This library must be on your MATLAB path.


sir these are few problem which i am facing in Matlab as well as in ISE 12.1,
Sir please suggest something, because i am in mid and i cant found which path to follow.

As per your suggestion i think my ISE didn't have DDC libraries,or i an unable to find it.
i had go through with few forums where i found that after ISE 9.1 xilinx remove some libraries from its futher editon.

Sorry if i write something wrong.
waiting for your precious suggestion.
Thank you in advance

Hi,

There is no library for DDC in either Xilinx ISE or Matlab. DDC is any application, you have to make this application by comprising all different modules according your need.

If you are following GSM standards, there is a demo available "GSM DOWNCOVERTER" in Simulink. It is also sythesizable (VHDL/Verilog). Check there! You can check the parameters of each block and replace them with your System Generator blocks, that is how you can get digital equivalent design in SImulink very quickly.

Hi mpatel
I m using ISE 10.1. Coregen available DDS/NCO has a maximum of 16 channels.
You are suggesting to generate a one 256 DDC (not 4*64). Is this possible?

mpatel said:

Hi


5. fine. You have 256 channels, means 256 carrier frequencies. You need to tune your NCO for each carrier frequency to convert the signal at zero-IF

6. 256 to 64*4 is fine but your design will be increased four times. You will have to place NCO, CIC and FIR four times. The only benefit is that your will get 4 parallel output channels. If you do not have such requirement, go for single DDC, it will save your FPGA area.

DO THESE:
1. Make a table for all 256 channels and their corresponding IF frequencies (carrier frequencies).
2. If you choose ADC undersampling then carrier frequencies of your channels will be changed. In that case repeat first step with new carrier frequencies.
3. These carrier frequencies will determine the necessary phase increment values of your NCO. Make a table for each phase increment values corresponding to its carrier freqencies.
4. Select 3rd order CIC and very narrow band LP FIR. If you are using CIC for downsampling then there will be multi-clock domain between CIC output and FIR input. Take care of that issue very well.

Added after 2 minutes:

If I am correct, with webpack license you can run paid IP cores for only one month after downloading into FPGA.

Added after 1 minutes:

Check www.opencore.org

You will get all your IP free of cost and they are technology independent also.

Click to expand...

Dear Mpatel sir,
Thank you very much for all of your kind support,but due to shortage of time i was unable to complete that DDC project,sorry for my faults and closing this thread, i was busy in my final semester exams, but now i think i need to complete this project and for that i need your help, i learned alot and what i realize if some one like you guide me then definitely we will deliver a *** product to the market which minimize a lot of work in communication network, sir please don't take it some other way i need some one like you here is my mail id if you found something good in me then please reply and if not then also reply and suggest me how could i change my self my mail id is: love.fru.85@gmail.com
Thank you in advance, waiting for your reply
Warm regards

what type of FPGA and RF front end board you used for your project?

Hi Asraf,
I am trying to design my own wideband RF front end and for FPGA i am using Xilinx Vertix5.....this is what i have....i am trying to design RF front end with bandwidth 50Mhz and IF frequency is 60 Mhz....so what kind of help u can provide me....as through my previous discussion you may know wha i am trying to make.
Waiting for your reply.
Thank you.