Verilog: Blocking Synthesis Issues

I am having trouble synthesizing blocking statements. I have a model MIPS processor and I am trying to introduce bugs to the processor. I am working with behavioral Verilog and synthesizing/compiling it with Synopsys Design Compiler. I am using ModelSim to check both the behavioral and structural code. I have attached two files. The original and bugged version. There are other modules but they all are unchanged from the original version.

I just changed the always block from nonblocking to blocking.

When I simulate the bugged behavioral processor before synthesis I notice errors in my test bench when compared to the original processor. However, when I try to simulate the synthesized version (structural) I get an output that matches the original processor. I assume the blocking is being turned into combinational logic. Thanks for any help. I have included only the behaviral code. There is a top processor that has other modules such as a reg file, decoder, and ALU. I am only changing the ALU.

Here is another post for more background info:


Thanks

Hi,

I just looked at your code.

Please note that there is no difference between the following two blocks, with respect to functionality. Both are combinational logic which synthesized to two mux.

reg out1;
reg out2;
always @(*)
begin
out1 <= sel1? I1: I0;
out2 <= sel2?out1:I3;
end

reg out1;
reg out2;
always @(*)
begin
out1 = sel1? I1: I0;
out2 = sel2?out1:I3;
end

Let me know if you have any questions.

Thanks for your reply. Maybe I am a little confused. In the blocking version of my code zero_out will be executed than the case statement. Where as the non blocking both will receive the old values. I understand why the example you gave are equivalent. If out1 and out2 were in separate always blocks for blocking a race condition would occur correct?

I get a different output when I compare the non blocking and blocking before synthesis. However, after synthesis the blocking and non blocking produce the same output.

Thanks for your help. Maybe you can clarify things for me.

Hi,

Yes. You are correct.
Though they may be different in the simulations, the synthesis treats them the same way - Just combinaitonal Logic.

Based on my observation,
I don't suggest this way.

Though there is parallel execution possible, there will be a delta delay between the execution of two statements.
So we can not really predict the result in simulations.

The best thing is to find alternate way to introduce bug into your ALU.

Please let me know if you are still missing something.

Thanks

Okay thank you now I understand. So it is best to avoid changing certain parts of my microprocessor from non blocking to blocking because Synthesis will treat it as combination logical. In the end the result will be the same. Thank you for clarifying this. It is difficult to introduce bugs in verilog and have it synthesize. Thank you for your help I will seek other ways.