interfacing AD7490 to FPGA problem, please help

Hi everyone,

i am currently writing a FPGA interface module to AD7490 and I get stuck on the 'first bit' reading problem at DOUT.

the problem is, there is an interval between holding down the CS and the first bit of DOUT comes out. this makes i can't get the DOUT data correctly.
so how can i deal with this?

Thank in advance,

Jerome G. JIANG

Hi Jerome,

I have experience using a state machine for this. You can synchronize state machine to system clock. In one of the states you set CS low and clear a counter which counts system clocks. Next state waits until counter reaches required delay and then advances to next state to begin clocking in serial data. I write in VHDL and may have some state machine code samples that could help. If you want you could post your code and I could look at it.

Cheers,
Scanman

Hi Scanman,

Thank you!

well, use a counter to count system clock is a great idea for a high speed system clk.

The problem is, the system clock is only 20Mhz and can't be modified, and I set the AD7490 to be 10Mhz.

as on the datasheet it says the delay is 14~20ns, so how can i do now? I attached my code below.

Best Regards,
Jerome JIANG
-------------------------------------------------------------------------------------
ScanCH_Delay: begin
ADC_Ctrl_Reg <={2'b10,ADC_Ch,10'b1100000000};
CS<=1'b1;
state <= ScanCH_Wait;
end

ScanCH_Wait: begin
CS<=1'b0;
Count <= 4'hF;
state <= ScanCH_Trans;
DOUT<=ADC_Ctrl_Reg[15];
ADC_DIN_Reg[15]<=DIN;
end

ScanCH_Trans: begin
ADC_DIN_Reg[Count-1]<=DIN;
DOUT<=ADC_Ctrl_Reg[Count-1];
if (Count==4'h0)
begin
case(ADC_DIN_Reg[15:12])
//case(ADC_Ch)
4'd0: CH0 <= ADC_DIN_Reg[11:0];
..............................
-------------------------------------------------------------------------------------------

scanman said:

Hi Jerome,

I have experience using a state machine for this. You can synchronize state machine to system clock. In one of the states you set CS low and clear a counter which counts system clocks. Next state waits until counter reaches required delay and then advances to next state to begin clocking in serial data. I write in VHDL and may have some state machine code samples that could help. If you want you could post your code and I could look at it.

Cheers,
Scanman

Click to expand...

Hi Jerome,

So you have T2 setup time ( 12ns ) from CS low to SCLK low.
T4 ( 40ns ) is DOUT valid after SCLK low.
I would suggest you synch the state machine to the 20Mhz clock:
always @ (posedge clock)
This gives 50ns aggregate timing.
Some FPGA chips allow clock multipliers does yours ?

Here is a rough example of a sequence:

State CS: Set CS low and set next state to T2_WAIT
(1 clock = 50ns). Allow for T2 setup time.

State T2_WAIT: set SCLK low and set next state T4_WAIT
(1 clock = 50ns). Allow for T4 data valid time.

State T4_WAIT: set SCLK high and set next state back to T2_WAIT
DOUT should be valid at this point.

This would generate a 10Mhz SCLK.
How are you generating the 10Mhz SCLK now?

You will need a process synched to the positive edge of SCLK for reading data from 7490 DOUT.
I'm a VHDL guy but I looked at some Verilog state machine code from this example:
https://www.asic-world.com/tidbits/verilog_fsm.html

Regards,
Scanman