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Unsynthesizable code Error in Synopsys Design Vision

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Manwe

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Hi,

I have a piece of Verilog code in an always block (with a posedge clock in the sensitivity list) that I am able to simulate but not synthesize using Synopsys Design Vision:
Code: 
ctrlList.sram[addr1] <= 0;

All statements in the always block are non blocking. Other accesses to the sram module work, and code for those parts can be synthesized. Can someone tell me what's going wrong? Thank you.
 

In rtl passing value is not allowed, you are using ctrlList.sram[addr1] <= 0;

you are passing value to sram[addr1] to zero it is only used in testbenches.






Regards,
Ravi.
 

    M

    Manwe

    Points: 2
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Manwe said:
Hi,

I have a piece of Verilog code in an always block (with a posedge clock in the sensitivity list) that I am able to simulate but not synthesize using Synopsys Design Vision:
Code: 
ctrlList.sram[addr1] <= 0;

All statements in the always block are non blocking. Other accesses to the sram module work, and code for those parts can be synthesized. Can someone tell me what's going wrong? Thank you.
Click to expand...

You are using "Cross Module access" which is called XMR - it is not allowed in Synthesis. You need to write to SRAM via addr/data interface/pins.

Regards
TeamCVC
www.cvcblr.com/blog
 

    M

    Manwe

    Points: 2
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