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BGA Problems & Placement of DDR3 termination resistances

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3Deye

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Hi,

I am asking about the best placement technique for the DDR3 termination resistances connected between DDR3 and FPGA IO traces, should they be near the FPGA or near the DDR3 ? I can place them beside both of the components with no problems, but I need a reccomendation :)

Another question, I use spartan 6 FPGA with 484 balls, but I couldn't route any trace from the inner balls to outer components ! Expedition rejects any attempt to route a trace between two balls because of the minimum distance of trace it allows (I don't know how to change it!), I read about BGA breakouts but I couldn't get applicable info.

I am using DxDesigner and Expedition.

Thank you.
 

What I do in this case is create a rule area. Here I can have a different set of clearances within rule area than the rest of the board.

1. In CES create a new scheme. Name scheme for this case "BGA fanout"
2. In "BGA fanout" scheme setup trace width and clearances that will allow you to route out of BGA.
3. Close CES
4. Draw a rectangular shape around BGA
5. edit properties of rectangle select "Rule Area"
6. Select "BGA fanout" scheme.

Now you can route out of BGA while not violating board clearances.

Regards,
Eda
 

    3

    3Deye

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With that many pins IMO it would be better to fan out and via to inner layers to get the tracks out.
 

Re: BGA Problems & Placement of DDR3 termination resista

What I do in this case is create a rule area. Here I can have a different set of clearances within rule area than the rest of the board.
Click to expand...
This solution is working great till now! I'll let you know my progress. Thanks eda.

I think you should place termination near to FPGA
Click to expand...
Thanks Ricky. After some -much more!- research, I found that we have two types of terminations, series and parallel, I am using parallel terminations. Also I found a memory controller document from xilinx for the FPGA I am using recommending placing the resistances near the DRAM if using parallel terminations which is my case, and near the FPGA when using series terminations.

With that many pins IMO it would be better to fan out and via to inner layers to get the tracks out.
Click to expand...
Thanks Mattylad. I am trying to fanout on the top layer now, If any problems occur, I'll try using the inner ones. Btw, I am using a 4-layer board and afraid that it wouldn't be suitable for this complex design!
 

Hi,
for good routings resultats is usefull to begin with power system of FPGA, then the Memory Lines_be care, it need very exact equivalent lengths between memory & FPGA!
Than are the I/Os of FPGA the next & only yet the rest of board, but I think your 4 layers will be eventually not enough for HF & EMC conform routings...
You can find good examples from Xilinx, & a EDA advertiser too: I will source for hes PCB design...
K.

Added after 55 minutes:

So, I have it yet_the layout is really a good routings example :)...:
 

    3

    3Deye

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Hi karesz :)

Thanks for the valuable tips and for the link.
 

Hi
The termination placement in a Design depends upon wheather it is a series or Parellel. The Series one must be place near to driver side as much as possible and the parellel one must be place near to source side.
 

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