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how to deal with high fanout net?

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lailiya

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how to deal the high fanout

hi, in my design, i find much delay spent on interconnect delay, especially on high fanout net. im cofused that where can i deal with these nets, in my verilog soruce file, or during sythesis, or during place/route. please give ur options, thanks! : :lol:
 

astro fanout

You can insert buffers.
 

astro high fanout synthesis

check your synthesis script:
1. have you assigned timing, clock, reset correctly
2. have you put the fanout constrains
3. have you put any net dont_touch
4. resynthesis again
5. some of the high fanout nets should be fixed in apr
 

Most of the back-end design tools can help you to solve this problem.Physical compiler and Astro can automatically detect and insert buffers on these high fanout nets to build high fanout trees.
Refer to PC & Astro user guide to get these command or you can type "help *fanout*" in shell.
 

In my experience, if I meet high fanout net:
During synthesis set_dont_touch_network and set_false_path to it.
all the work will be done in Layout tool:there are special command for high fan-out net just as CTS
 

I think Astro can handle it perfect. This issue depends deeply with the layout so you can let Astro help you
 

Another option where you can control the numbers of fanout is in synthesis level. You can tell synthesis tool (i.e DC) to set a value for the max_fanout.

Example:
dc_shell-t > set_max_fanout ##
 

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Hi,

Sometimes it makes sense to not buffer up a net
during synthesis, but rather to leave it for layout
and then use a clock tree insertion tool to buffer it.
I have seen this option excercised for scan enable
signals and async. reset trees.
 

yes, i try to buffer a general high fanout net after placement in Physical Compiler, i use command create_buffer_tree, but it use too many buffers, even include delay cells, im confused about this result, whether should i buffer up high fanout net during layout?
 

crystal said:
Another option where you can control the numbers of fanout is in synthesis level. You can tell synthesis tool (i.e DC) to set a value for the max_fanout.

Example:
dc_shell-t > set_max_fanout ##
Click to expand...

set_max_fanout $number of fanout permitted,

for the network that will dealed during P&R, better set_dont_touch and set_ideal_network
 

you can synthesize high fanout nets into buffer tree during place & route stage.



lailiya said:
hi, in my design, i find much delay spent on interconnect delay, especially on high fanout net. im cofused that where can i deal with these nets, in my verilog soruce file, or during sythesis, or during place/route. please give ur options, thanks! : :lol:
Click to expand...
 

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