Need help on programing an FSM on Spartan 3E 1600

Hi, i`m trying to crate an FSM on a Spartan 3E-1600, an so far I didn`t do nothing. I`ve found some codes on internet but most of all are wrong. In my last reserches i`ve found an examples describing an FSM but dont know what its doing, i`m using Xilinx ISE 11 and the HDL is Verilog. I`m still a beginer with FPGA`s and i have a project in few months and want to create something. If anyone knows someting about this program please post an answear, it will be nice to hear from you guys. And i`m needing an .UCF file cuz i dont know how to crate it.



P.S. I`m sorry for my bad english, hope my mistakes in text were few and you could understand what i want.

Hi, I also have spartan 3e-1600 development kit, I want to know is there any book which is particularly written for vhdl code examples for this kit.

Added after 32 minutes:

In order to correctly implement any design on fpga kit you must follow proper procedure (i.e first go through the user guide of that kit).User constraints file contain many important constraints of the fpga design for e.g;
pin assignment
voltage level of I/O pins(i.e LV CMOS,TTL)
timing considerations any many more things,

Knowledge of PIN assignment, clock resources etc can be known from the user guide.If you are a beginner in this field then these books:
1). FPGA Prototyping by VHDL Examples(this book is particluarly for spartan 3 board)
2). Circuit Design with VHDL Volnei A. Pedroni
are very good books for you, but they use VHDL language not verilog.


Regards,
Zafir Hafeez

Thank you for your replay. Well I want to know to what that codes do, what they suppose to do. Again many thanks for your replay.

Thank you again for your post. Well i`ve tryed to implement an UCF file for this code and i`ve declared my ouputs ports on LEDs and inputs on buttons, clk on the on-board clock and reset on a button. So far worked something, 3 led`s lighted up, was kind nice to see that worked. So far i dont know what that cod does and dont know what to expect from him. hehe i`m a newbie at verilog.

Thanks again.