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Having trouble dividing clock by two (VHDL)

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uoficowboy

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Hi - I'm trying to learn VHDL. I'm using ISE Webpack 12.1 with ISim. I want to make a simple bit of code that divides a clock signal by two. My idea was to invert the output of entity on every rising edge of the input clock.

The code is below, and I've attached a screenshot of the simulation. The problem is that the output goes undefined every other clock cycle.

Can anybody tell me what I'm doing wrong? I suspect there are better ways to do this, but I'd really like to figure out what is wrong with this code.

Thanks!

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DivideClockBy2 is
    Port ( Clk : in  STD_LOGIC;
           ClkOut : out  STD_LOGIC);
end DivideClockBy2;

architecture Behavioral of DivideClockBy2 is
	signal ClkOutInt : STD_LOGIC := '0';
begin
	ClkOut <= ClkOutInt;
	process (Clk)
	begin
		if (Clk'event and Clk = '1') then
			ClkOutInt <= not ClkOutInt;
		else
			ClkOutInt <= ClkOutInt; --not sure if this is needed, but it doesn't seem to change anything
		end if;
	end process;

end Behavioral;
 

I don't see any problem in ise 11.5 simulator and more over the RTL schematic of the your code does what you intend. I have attached the Behavioral and Post-Route simulation no problems, the o/p is as you would expect.
 

    U

    uoficowboy

    Points: 2
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actually you dont need the clkoutint signal. you can drive the clkout directly.
if clk'event and clk = '1' then
clkout <= not clkout;
end if;
end process;

also you should put the clkoutint signal in the processes sensivity list
process(clk,clkoutint)
....
 

    U

    uoficowboy

    Points: 2
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zula said:
actually you dont need the clkoutint signal. you can drive the clkout directly.
if clk'event and clk = '1' then
clkout <= not clkout;
end if;
end process;

also you should put the clkoutint signal in the processes sensivity list
process(clk,clkoutint)
....
Click to expand...
Hi - I thought you couldn't read outputs. Doesn't inverting clkout like that require you to first read it in?

I believe buffers can be read in, but I haven't had any luck with buffers just yet.

Why does clkoutint needs to be in the process sensitivity list? I thought you only need signals and variables in the sensitivity list that you want to have cause the process to be run? I mean, I don't need the code inside the process to be run if clkoutint is changed, I think?

Sorry if I'm totally off here. I'm very new to VHDL but I'm very interested in learning it.

Added after 1 minutes:

barath_87 said:
I don't see any problem in ise 11.5 simulator and more over the RTL schematic of the your code does what you intend. I have attached the Behavioral and Post-Route simulation no problems, the o/p is as you would expect.
Click to expand...
So, could this perhaps be a bug with ISE 12.1/ISim? Now I'm confused!
 

oh yes clkout is the output. if you change it to inout or buffer you can read it.
processes sensivty list like a key. if sensivty signal changes the process executed otherwise some of problem occurs.
 

Can send in your test bench ...may be there is a problem there.
 

barath_87 said:
Can send in your test bench ...may be there is a problem there.
Click to expand...
Hi - my test bench is very simple. Completely auto-generated by ISE
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY DivideClockBy2TB IS
END DivideClockBy2TB;
 
ARCHITECTURE behavior OF DivideClockBy2TB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DivideClockBy2
    PORT(
         Clk : IN  std_logic;
         ClkOut : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Clk : std_logic := '0';

 	--Outputs
   signal ClkOut : std_logic;

   -- Clock period definitions
   constant Clk_period : time := 10 ns;
   constant ClkOut_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DivideClockBy2 PORT MAP (
          Clk => Clk,
          ClkOut => ClkOut
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 
   ClkOut_process :process
   begin
		ClkOut <= '0';
		wait for ClkOut_period/2;
		ClkOut <= '1';
		wait for ClkOut_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for Clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
 

According to VHDL syntax rules, the testbench couldn't by compiled without errors, because ClkOut is driven both by the DUT and ClkOut_process. I wonder how this strange code can be auto-generated?
 

FvM said:
According to VHDL syntax rules, the testbench couldn't by compiled without errors, because ClkOut is driven both by the DUT and ClkOut_process. I wonder how this strange code can be auto-generated?
Click to expand...
Oh my goodness. Serves me right for not looking at the auto-generated code carefully! Originally ClkOut had been a buffer - would that have caused ISE to create such a strange TB?

Regardless - I just commented out that process and suddenly the whole thing works. Great catch!
 

FYI ...

I got the same code when I auto-generated it from ise 11.5 I commented out the section where clkout was getting driven and then ran the simulation.
 

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