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Well, there is long answer to your question. so I didn't write here. I am giving links
just follow that, it will be useful for you to understand the Cortex architecture and how it differs from ARM 7 TDMI.
ARM 7 is one of the classic ARM processors.
It uses assembly instructions.
ARM Cortex is the new ARM processors, they are based on ARM7. The new thing they are multi-core and use a programming interface other than assembly.
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Amr Ali
Cortex is the result of a new naming convention from ARM. In the past ARM has numbered their cores, ARM7 very successful, ARM8 a flop, ARM9 very successful, ARM10 a flop, ARM11 very successful, and what now?
Call it ARM12 and prepare for another flop? Call it ARM13 and have all the superstitious people go bananas? They had a problem.
Now some wise guys came up with the idea to call ALL future cores from ARM Cortex and a suffix.
There is Cortex-A for applications processor, the high end running > 1 GHz
There is Cortex-R for real-time processor, the mid range 400-600 MHz
There is Cortex-M for microcontroller the low end running < 200 MHz
Watch closely Cortex-A-R-M spells ARM again
With Cortex, new devices have an extended instruction set, most important Thumb2. All Cortex devices support the more efficient Thumb2, smaller code and a mix of 16/32-bit instructions.
For a list of many Cortex-M based devices and articles check out this site: **broken link removed**
Other important improvements of Cortex-M over ARM7
Faster and more predictable interrupts
Better debugging support
Lower power
More performance at the same clock speed
and many more
Don't forget the fact that Cortex specifies the NVIC (Nested Vectored Interrupt Controller) and SYSTICK (system TICk timer). The ARM parts didn't and so each licensee had to bolt on their own, making for non-compatibility between ARM chips.
With the NVIC and SYSTICk standardised in all Cortex parts it makes it much easier to port operating systems from one to another.
The SYSTICK is a 32 bit timer integrated in the CORTEX core and so is identical in all CORTEX based chips.
A general purpose timer is a peripheral which can be 8 bit, 16 bit or 32 bit depending on implementation. This is chip/manufacturer dependent and so incompatible between devices. Also using such a timer as system tick means that it is no longer available for other functions which it may be able to do (eg. PWM etc.).
Having a SYSTICK means that SW is compatible and no general purpose timer is needed by the system TICK. An OS will generally require one timer (SYSTICK) for its periodic interrupt and other timing functions.
Nesting allows interrupts to be allocated unique interrupt priorities so that higher priority interrupts can interrupt lower priority ones. A VIC will allow one interrupt to be vectored to but no further to be executed until the first has completed. The ARM had limited nesting since the FIQ could interrupt the IRQ. Many manufacturers did add NVICs to their ARMs by using their own tricks but each one was a proprietary design and again not compatible across devices. The Cortex has full capabilities integrated into the core so that it is now much more powerful and standardised across all devices.
But it saves using a general purpose timer, leaving this free for other uses, and SW for the SYSTICK is compatible on all Cortex based devices - thus making changing processors easier. As you point out - this is not absolutely necessary but it is a nice advantage.
The tail-chaining is an optimisation when one interrupt completes and another needs to be taken. Rather than popping all registers saved by the first interrupt and then recognising that another is waiting and then pushing them again it can immediately execute the following interrupt (saving 8 unnecessary register pops and pushes).
The previous ARMs supported Thumb and ARM modes but needed to switch between them. Generally parts of code were compiled in either ARM or Thumb - or complete projects in one of them. ARM was faster but required more space and Thumb were 16 bit instructions - more limited but code-efficient.
The Cortex processors do not support ARM mode but do support almost all original Thumb instructions. In addition they have new Thumb-2 instructions which are a mixture between 16 and 32 bit - effectively optimised for speed and size. The result is about Thumb size code with speeds outperforming the original ARM instruction set.
Note that you can get all details from the Cortex technical reference manuals which are available from ARM.
Hi,
you are correct, Cortex-M does not offer ARM Mode, however Cortex-R and Cortex-A do offer ARM Mode.
Cortex-M only offers Thumb2 which is a superset of Thumb mode. So, in that sense it offers Thumb + Thumb2
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