Why a I overshoot when CC to CV mode in linear bat charger

I design a linear battery charger.
There is a current overshoot when CC(constant current) to CV(constant voltage) mode transition.
The charger structure reference the LTC4062's datasheet. the CC amp and CV amp share one current shink.
When I test the charger, I find the current overshoot. but simulate cann't find this issue.
anyone know root cause of this issue.
I design the max charge current about 1.5A.
I test find. There is an overshoot when charge current larger than 1.2A.
Charger have not overshoot when charger current equal and less than 1.1A

I analyze the test result, I find the current mirror loop cann't follow this I overshoot.

I design the charger:
current loop: gain 60db, bandwidth about 200K,
CCloop: gain 70db bandwidth about 20K
CVloop: gain 70db bandwidth about 10K (ESR of battery and cap of battery, will zero and pole cancel)
When Vbat rise, the cc gain will reduce, and Cv loop gain increase.

Added after 10 minutes:

cds.linear.com/docs/Datasheet/4062fb.pdf
4062 datasheet.
block diagram in page8.

Re: Why a I overshoot when CC to CV mode in linear bat charg

charger circuit and test result

I have found the root cause and FIB verified.

Could you share your experience here?
It will be very nice for you!

There are two loops to control the bigPMOS's gate.
For CC
The the whole loop gain is Gain_CC-Gain_CV,
For CV
The the whole loop gain is -Gain_CC+Gain_CV
When the battery close to 4.2, the whole loop gain will close to 0, but at that time the current mirror loop will force the current doesn't fly(overshoot or undershoot). In order to save the die size the big Power MOS work in the linear region, that time the layout parasitic resistor (Rds for big MOS and mirror MOS) will be critical. When the CC to CV the loop most lilke open(as loop gain almost to 0) only the current mirror loop clamp the charger current.
So the mirror MOS Rds(MOS's Rds + layout path parasitic) is larger, the current will overshoot, If that is smaller charge current will be undershoot.
The good layout need matching Rds between the mirror MOS and power MOS.