[SOLVED] vgs current generator

Hi All,

Please, I am trying to design the following circuit. It generates a current IR1, proportional to VGS1.
This circuit was proposed in the following reference:¨ A low-voltage Low-Power voltage reference Based on subthreshold MOSFET.¨ G. Giustolisi, G. Palumbo. JSSC 2003.
I have just designed it. It works properly. However, I don't understand how the feedback work.

could somebody give a intuitive view about how it works?

Thank you very much,

Best wishes,

Maybe a simplification will show you the feedback path.

Good afternoon Joannes!

Thanks very much for your suggestion. It is very nice how a simple change in the way of seeing the circuit, makes it to be easier to be understood.

The paper - that proposes this circuit - reports that the dominant pole of this circuit is given by:

wGBW1 = [(gm1*gm2*R1)/Cc1]*(S4/S3)

I have some doubts about it. If possible, could you give some insight about it? I would be very very very glad.

(1) Do you know how they calculated this?
I can draw the small signal model for all transistors. After calculating the transfer function, I will discover the poles and zero. However, I dont know which are the input and output of this circuit. So, how can I calculate the transfer function?

(2) The author suggests setting Cc1 in order to maintain wGBW1 well below the value of other remaining poles. Following this recommendation, my circuit will have improved gain-bandwidth product.
I did not understand why the author is talking about gain-bandwidth product when this output voltage provided by this circuit is DC. What would I improve in the circuit if I follow this recommendation?

(3) How could I measure the stability of this circuit? And check if the circuit is stable, and its phase margin?

Thanks very much again,

Best wishes

palmeiras said:

The paper - that proposes this circuit - reports that the dominant pole of this circuit is given by:

wGBW1 = [(gm1*gm2*R1)/Cc1]*(S4/S3)

(1) Do you know how they calculated this?
I can draw the small signal model for all transistors. After calculating the transfer function, I will discover the poles and zero. However, I dont know which are the input and output of this circuit. So, how can I calculate the transfer function

Click to expand...

The small signal model is the correct way of proceeding. I would use the resistor voltage as the input node and the M2 gate as the output node.

palmeiras said:

(2) The author suggests setting Cc1 in order to maintain wGBW1 well below the value of other remaining poles. Following this recommendation, my circuit will have improved gain-bandwidth product.
I did not understand why the author is talking about gain-bandwidth product when this output voltage provided by this circuit is DC. What would I improve in the circuit if I follow this recommendation?

Click to expand...

Even though the circuit goal is to produce a DC voltage, it has its dynamics: how fast do you correct for variations of the output voltage? Moreover, it is a feedback system, so you want it to be stable...

palmeiras said:

(3) How could I measure the stability of this circuit? And check if the circuit is stable, and its phase margin?

Click to expand...

I would break the loop at the gate of M2 and use the usual control theory techniques to check stability...

Hi JoannesPaulus!

Thanks so much.

Regarding the discussed points, if possible, could you be more clear about:

(1 ) : Could you explain the reason why you consider the resistor voltage as input node, and m2 gate as the output node?

a) Device M2 also acts as amplifier (exactly as M1). Could I consider its gate node as input, and its drain as output node?

b) What is the rule to choose the point where breaking the loop?

(3) : About the usual control theory technique to check stability; could you give a example of how you would analyze this?

In case of amplifiers, I draw the bode curve and I check the phase when the gain is equal to the unity. The phase must be positive and higher than 45 degrees, at least, to guarantee the stability. But I dont know what to do in this case.

Thanks again…

Best wishes.

Hi.

JoannesPaulus said:

Maybe a simplification will show you the feedback path.

Click to expand...

One remark. Non-inverting input of the amplifier must be connected to a voltage source Vgs instead of ground.

palmeiras said:

The paper - that proposes this circuit - reports that the dominant pole of this circuit is given by:

wGBW1 = [(gm1*gm2*R1)/Cc1]*(S4/S3)

I have some doubts about it. If possible, could you give some insight about it? I would be very very very glad.

(1) Do you know how they calculated this?
I can draw the small signal model for all transistors. After calculating the transfer function, I will discover the poles and zero. However, I dont know which are the input and output of this circuit. So, how can I calculate the transfer function?

Click to expand...

wGBW1 (gain-bandwidth product) is defined as product of DC gain and bandwidth (BW, -3 dB frequency): wGBW = [DC gain]*[BW].

You asked where was input and where was output, or in other words how is defined gain in this circuit. This circuit is DC current source with feedback network. The only gain which makes sense in this circuit is loop gain (LG). It can be found as product of gain of the voltage amplifier (M1, IB), transconductance gain of transconductance amplifier (M2, M3), gain of the current mirror (M3, M4) and equivalent impedance to ground from node where gate of M4 and R1 are connected : LG = [gain of M1, IB]*[transconductance of M2, M3]*[gain of M3, M4]*[output resistance of (M4, R1)]. Obviously DC loop gain is equal to products of DC gains. DC gain of (M1, IB) is gm1*ro1. DC transconductance of (M2, M3) is gm2 (more precisely gm2*ro2/[ro2 + (1/gm3||ro3)], but ro >> 1/gm in most cases). DC gain of M3, M4 is equal to ratio of aspect ratios of M4 and M3 - S4/S3. Output resistance of (M4, R1) is R1||ro4. These results yields DC loop gain = ro1*gm1*gm2*(R1||ro4)*(S4/S3).

Next step is determination of bandwidth of this circuit. I don’t suggest you to use direct small-signal analysis for this purpose. It's extremely hard work (when number of transistors is greater than one). There are much simpler intuitive methods which are more appropriate for hand analysis. One of such methods is described in Razavi's "Design of Analog CMOS Integrated Circuits" (section 6.1.2 "Association of Poles with Nodes"). Application of this method gives three poles: |p1| = 1/(ro1*Ceq1), |p2| = 1/(ro4||R1*Ceq2), |p3| = 1/[(1/gm2||1/gm3)*Ceq3], where Ceq are equivalent capacitances to ground from corresponding nodes. ro >> 1/gm and Ceq2 ~ Ceq3, so |p2| << |p3| and third pole will be ignored. If we assume that ro4 >> R1 and Cc1 >> all other capacitances at this node, than p1 will appear to be dominant one (also note that equivalent resistance to ground from node where gate of M4 and R1 are connected will be equal to R1 instead of (R1||ro4)). If the circuit has only one dominant pole and no dominant zeros, -3 dB frequency (bandwidth) will be equal to the frequency of that dominant pole. Thus bandwidth of this circuit is equal to BW = 1/(ro1*Cc1) rads/s.

wGBW1 = [DC gain]*[BW] = [ro1*gm1*gm2*R1*(S4/S3)]*[1/(ro1*Cc1)] = gm1*gm2*R1*(S4/S3)/Cc1.

palmeiras said:

(2) The author suggests setting Cc1 in order to maintain wGBW1 well below the value of other remaining poles. Following this recommendation, my circuit will have improved gain-bandwidth product.
I did not understand why the author is talking about gain-bandwidth product when this output voltage provided by this circuit is DC.

Click to expand...

Decreasing value of dominant pole (and thus decreasing value of gain-bandwidth product) increases stability of the circuit.

palmeiras said:

What would I improve in the circuit if I follow this recommendation?

Click to expand...

Increase Cc1 until phase margin of the loop reaches some acceptable value (typically 45 or 60 degrees).

palmeiras said:

(3) How could I measure the stability of this circuit? And check if the circuit is stable, and its phase margin?

Click to expand...

Loop gain simulation

If your simulator is spectre, you can use stability analysis.

Hi dedalus,

Thank you so much for your very detailed explanation!

Nice recommendation about `Association of Poles with Nodes` in the Razavi book. I will study this chapter and then, I will be able to understand how you estimated the values of the poles.


I only did not understand two things:

(a) You told that the transconductance of (M2, M3) is more precisely described by gm2*{ro2/[ro2 + (1/gm3||ro3)] }. I didn’t see why there is a second term (r02/…).

Because, when one calculates the transconductance of amplifiers, the output is shorted and therefore is given by Gm =Io/Vi. (Output current/input voltage). For instance, in the case of M2, replacing it for small-signal model, one can see that the output resistance at the drain of M2 is given by ro2||ro3||1/gm3. However, the transconductance of M2 does not take this into account.


(b) I simulated the stb (Stability) analysis using Cadence. My first results shows instability when the phase margin was negative. After increasing the value of Cc1, the phase margin became 60 degrees.

But my question is: why didn’t my transient simulation show unstable output voltage, in the first case simulation (without compensation capacitor)?

I replaced my Vdd supply voltage for a ramp voltage source, and the results show a stable output. That is… Many times I trusted in the transient simulation to check if my circuit is stable. Is this concept wrong?

Thanks you very much for this great discussion.

Best wishes,

Hi palmeiras

palmeiras said:

(a) You told that the transconductance of (M2, M3) is more precisely described by gm2*{ro2/[ro2 + (1/gm3||ro3)] }. I didn’t see why there is a second term (r02/…).

Because, when one calculates the transconductance of amplifiers, the output is shorted and therefore is given by Gm =Io/Vi. (Output current/input voltage). For instance, in the case of M2, replacing it for small-signal model, one can see that the output resistance at the drain of M2 is given by ro2||ro3||1/gm3. However, the transconductance of M2 does not take this into account.

Click to expand...

Output current of (M2, M3) is current that flows into M3 (M2 is actually transconductance amplifier and M3 is load). Short-circuit forward transconductance (Gm) is defined as ratio of output current to the input voltage with short-circuited output (in other words with zero load, \[G_m = \frac{I_{out}}{V_{in}}, R_{load} = 0\]). Since resistance of M3 isn't equal to zero, transconductance gain of (M2, M3) is not equal to the short-circuit transconductance.

I attached figure with small-signal model of M2, M3 to illustrate this difference.

\[G_m = \frac{I_{out1}}{V_{in}} = g_{m2}, R_o = r_{o2}, R_{load} = \frac{1}{g_{m3}} || r_{o3}\]

\[G = \frac{I_{out2}}{V_{in}} = \frac{I_{out1}}{V_{in}} \cdot \frac{R_o}{R_o + R_{load}} = G_m \cdot \frac{R_o}{R_o + R_{load}} = g_{m2} \cdot \frac{r_{o2}}{r_{o2} + \frac{1}{g_{m3}} || r_{o3}}\]

Hi dedalus,

Thanks you again!

Best wishes,