jacobiLL
Newbie level 5
![Newbie level 5](/styles/images/ranks/blevel2.gif)
Hi ,all.
I have a asynchronous FIFO in my design, I found the simulation results is different between RTL and netlist. It is caused by the asynchronous FIFO, at the mistake time, the read clock and the write clock is very close(0.5ns), the netlist output is late than the RTL output.
I wonder to know is it unavoidable for the asynchronous FIFO? Use Gray code can only reduce probability of this unexpected error.
I have a asynchronous FIFO in my design, I found the simulation results is different between RTL and netlist. It is caused by the asynchronous FIFO, at the mistake time, the read clock and the write clock is very close(0.5ns), the netlist output is late than the RTL output.
I wonder to know is it unavoidable for the asynchronous FIFO? Use Gray code can only reduce probability of this unexpected error.