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Cadence DRC error messages

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bifurcate

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Hi
I am learning to use Cadence by designing an OTA.
I'm a bit stuck understanding what these error messages mean in the DRC checker.
if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following:

1. Welnotr_StampErrorFloat
(NWEL is highlighted)

2. 4:16n Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted

3. 4:17N Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
all pmos diffusion highlighted

Also, just checking
I need to connect the bulk of each pMOS transistor to VDD, would this be the NWEL?
and the bulk of the nMOS transistors to VSS, would this be the substrate?

thanks
Andrew
 

Hi Andrew!

Some errors are difficult to understand without help of process design kit manual. You need to check there what these errors would be.
Error 1 seems to be error in the connection of NWELL of your PMOS devices. Make sure to connect the NWELL to VDD.Yes... this is the bulk of PMOS.

The bulk of NMOS is the substrate, and it should be connect to VSS or ground.

You can ask other doubts
 

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    bifurcate

    Points: 2
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bifurcate said:
1. Welnotr_StampErrorFloat
(NWEL is highlighted)
Click to expand...

The highlited nwell (probably of PMOS ) is not connected to VDD or highest potential .... you need to connect it .. using ntap

bifurcate said:
2. 4:16n Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted
Click to expand...
This is latchup error for nmos ..... and there is no bulk connection for highlited nmos...provide bulk connection and connect to gnd. ...
bifurcate said:
3. 4:17N Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
all pmos diffusion highlighted
Click to expand...
This is latchup error for pmos ..... and there is no bulk connection for highlited nmos...provide bulk connection and connect to vdd
. ...
bifurcate said:
Also, just checking
I need to connect the bulk of each pMOS transistor to VDD, would this be the NWEL?
and the bulk of the nMOS transistors to VSS, would this be the substrate?
Click to expand...
right.


-Deepak.


[/quote]
 

    B

    bifurcate

    Points: 2
    Helpful Answer Positive Rating
Thankyou both
I will have a crack at it this afternoon....then start thinking about the LVS!
 

Yes - got it sorted tonight
passed DRC and LVS checks too
so Thankyou again!!

now I have to think about shielding, will have a search for tips.
 

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