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questions about Cadence wire name

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hmsheng

hmsheng

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I have a bus with 32 bits. The 24 MSB bits connect to gnd, and the 8 LSB bit connect to a<7:0>. We can give a wire name as gnd,gnd,...,gnd,a<7:0>. There are totally 24 gnds in the wire name. But this way is very tedious.

In verilog, there is a way like this: 24{gnd},a<7:0> .

Is there a simple way to name the wire in Cadence?

Regards,
hmsheng
 

Either <*24>gnd,a<7:0>
or gnd*24,a<7:0> should work.

Why would you need 24 gnd wires in a bus? ;-)
 
erikl said:
Either <*24>gnd,a<7:0>
or gnd*24,a<7:0> should work.

Why would you need 24 gnd wires in a bus? ;-)
Click to expand...

I have a behaviour model of bin2dec with 32bit input, only the 8LSB connects to the output of another block, the 24MSB should be connected to gnd. That's it.

BTW, <*24>gnd,a<7:0> works, but gnd*24,a<7:0> doesn't.
 
hmsheng said:
BTW, <*24>gnd,a<7:0> works, but gnd*24,a<7:0> doesn't.
Click to expand...
Thanks for your feedback - and for having clicked "helped me" !
 

    hmsheng

    hmsheng

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