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fix hold time violations

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Mamdouh

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how can i fix hold time violations resulted from DFT scan insertion using multiplexed flip flops on compiling the design normally no violations but when inserting DFT scan hold time violations occur
 

1) hold violations are fixed post CTS

2) make sure your clocks are faily balanced on the paths you are fixing. If so add buffers to fix the violations

3) if your scan domain crosses multiple asynchronous functional clock domains you may need to redo CTS with these domains balanced -or- rodo how you define your scan chains
 

can you please explain more ??!!
 

After scan insertion, the scan out pins of flops get directly connected to the scan in pin of the next flop. Since there is no logic in between, this can lead to hold time violations.

If you see these violations after synthesis, don't worry about them yet. They are normally fixed after clock tree synthesis (CTS) when you fix all other hold violations.

If you see them post CTS, check the clock skew on the violations to be sure CTS did a good job. Otherwise you may end up adding too many buffers.

Does this help? Also, if you see these violations post CTS, how many seperate clocks are you balancing?
 

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    Mamdouh

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