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Mamdouh said:How can I generate a VCD file?
nsingh95 said:Hi,
Inorder to generate a vcd file , you have to use following key words in your test bench file ... ie <testbench top filename.v>:
type :
initial
dumpfile("module_name.vcd");
initial
dumpvars();
If you simulate with this logic you will surely get the vcd file.
Mamdouh said:nsingh95 said:Hi,
Inorder to generate a vcd file , you have to use following key words in your test bench file ... ie <testbench top filename.v>:
type :
initial
dumpfile("module_name.vcd");
initial
dumpvars();
If you simulate with this logic you will surely get the vcd file.
how can i write these lines in vhdl format
Added after 1 hours 4 minutes:
to be specific i want to generate vcd file from testbench.vhd using xilinx ?
$comment
File created using the following command:
vcd file ana.vcd -dumpports
$end
$date
Thu May 06 22:35:44 2010
$end
$version
dumpports ModelSim Version 6.5
$end
$timescale
1ps
$end
$vcdclose
#1000
$end
Mamdouh said:first thanks very much i used the commands in the manual and here's the generated vcd file i know there's something wrong but i cant figure it out??
$comment
File created using the following command:
vcd file ana.vcd -dumpports
$end
$date
Thu May 06 22:35:44 2010
$end
$version
dumpports ModelSim Version 6.5
$end
$timescale
1ps
$end
$vcdclose
#1000
$end
Mamdouh said:first thanks very much i used the commands in the manual and here's the generated vcd file i know there's something wrong but i cant figure it out??
$comment
File created using the following command:
vcd file ana.vcd -dumpports
$end
$date
Thu May 06 22:35:44 2010
$end
$version
dumpports ModelSim Version 6.5
$end
$timescale
1ps
$end
$vcdclose
#1000
$end
wlf2vcd (or something similar)