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Hi,
you should not give any delay in RTL.If it is necessary then use some register tranfer logic i.e. reg a <= reg signal;
reg b <= reg a; .... and so on .... as per your requirement.
OR,
You first generate the netlist without using any intra delay.And after the netlist generation you can give delay in netlist but only for your simulation purpose.
If you consider the hardware aspect of it the intra delay must not be give.
Hi,
you should not give any delay in RTL.If it is necessary then use some register tranfer logic i.e. reg a <= reg signal;
reg b <= reg a; .... and so on .... as per your requirement.
OR,
You first generate the netlist without using any intra delay.And after the netlist generation you can give delay in netlist but only for your simulation purpose.
If you consider the hardware aspect of it the intra delay must not be give.
Thanks for ur answer.
i write like this,and the delay is used for simulation,
but i want dc ignor the warning,and there is no warning(style ver-130) in the log file.
I can remove it by sed,but i dont want to do like that.
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
cout<=0;
sum<=0;
end
else
{cout,sum}<= #3 tempa+tempb+tempc;
end
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