A CTS error: The net clk is driven by more than one driver

Hi All,

I got an error when I do clock tree synthesis in Encounter

**ERROR: (SOCCK-218): The net clk is driven by more than one driver. Please correct your clock specification file to exclude the net.
**ERROR: (SOCCK-211): CTS was unable to trace clock clk.

I checked the clock specification file, but I do not have any clue where causes this multiple drivers. Below is my clock spec. Please give me a help

AutoCTSRootPin clk
Period 5ns
MaxDelay 0.5ns # set_clock_latency
MinDelay 0.5ns # set_clock_latency
MaxSkew 200ps # set_clock_uncertainty
SinkMaxTran 200ps # set_clock_transition
BufMaxTran 200ps # set_clock_transition
Buffer CKBHVTD2 CKBHVTD3 CKBHVTD4 CKBHVTD6 CKBHVTD8 CKNHVTD6 CKNHVTD8 CKNHVTD12 CKNHVTD16 CKNHVTD0
NoGating NO
DetailReport YES
SetDPinAsSync YES
#SetIoPinAsSync NO
RouteClkNet YES
PostOpt YES
OptAddBuffer YES
#RouteType specialRoute
#LeafRouteType regularRoute
ThroughPin
END

I would suggest not taking Encounters advice and excluding your clock net so don't worry about the clock spec. It sounds like the issue is in your design itself. Check the net 'clk' to see if it has more than one driver.


try doing a check_design -all and look to see if it flags multi driven nets. You can also try report_net -net clk, i think that shows connected sources/sinks. If not, find out if something else is driving clk and fix it.

Re: A CTS error: The net clk is driven by more than one driv

Above is correct.

And you can check your netlist, make sure that pin direction related with this clock is correct and does not make any race.

Re: A CTS error: The net clk is driven by more than one driv

I used checkDesign, clk is not in the list of multi-driven nets.

when I use report_net -net clk, I got an error:
'early' data can not be reported in 'late' timing analysis mode, to report 'late' data use '-late' option or use 'report_timing -early' to run 'early' timing analysis

Then I used Tool-Design browser to check the clk net. There are two pins associated with the net clk. One is clk (input) - clk and the other is IOCELL42/PAD (bidir). I think this bidirectional pin causes the multiple drive. This pin from the I/O pad. In my netlist, I have a top module where instanciates both I/O cells and the core design cell. I have my clock connected like something shown below.

module top_module (port list);

....

input clk;

wire IO42;

PRUW1216SCDG_25 IOCELL42( .I(1'b0),.DS(1'b1),.OEN(1'b1),.PAD(clk),.C(IO42),.PE(1'b1),.IE(1'b1));

core_design core (.clk(IO42) ....);

for I/O cell, PAD->C is input path. Could you please tell me whether it is the correct way to connect I/O with the core cell. From the layout, the C port of the I/O pad is not connected to the core cell.

Also I found there are a lot of unplaced I/O pins, how I can place those I/O pin. I have already load I/O assignment file which assign all I/O pad cells.

Thank a lot

If I understand correctly, "clk" is the top level port on the netlist which is connected to IO pin PAD of the IOCELL and the C pin is an output of the IOCELL going to the entire design. Thus the path is clk->PAD->C->core.
In this case, defining the RootPin as clk should be ok, but I didn't understand why you said the "C port of the I/O pad is not connected to the core cell" ? Then how is the clk propagated to the entire design? Does "core_design core (.clk(IO42)....);" not mean that the C port is connected to your core_design? Or am I missing something here.

Also, if PAD is defined as an IO (i.e. inout PAD) in the pad cell definition, you also need to define the top level input in the netlist as inout clk; instead of input clk;

Re: A CTS error: The net clk is driven by more than one driv

Hi D Saurabh,

You are right, the path is clk->PAD->C->core cell. Actually I checked the layout, C pin was connected to the core cells. Sorry for the confusion. But when I do any timing analysis, I got nothing on the report like below

------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 0.000 | N/A | N/A | N/A | N/A | N/A |
| TNS (ns):| 0.000 | N/A | N/A | N/A | N/A | N/A |
| Violating Paths:| 0 | N/A | N/A | N/A | N/A | N/A |
| All Paths:| 0 | N/A | N/A | N/A | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+

+----------------+----------------------+---------+
| | Real | Total |
| DRVs +---------+------------+---------|
| | Nr | Worst Vio | Nr |
+----------------+---------+------------+---------+
| max_cap | 0 | 0.000 | 0 |
| max_tran | 0 | 0.000 | 0 |
| max_fanout | 0 | 0 | 0 |
+----------------+---------+------------+---------+

If you directly connect clk to the core cells, I can get something like all paths number, how much violation paths and so on. So I think somewhere should be disconnected for clk net.

Thanks

Re: A CTS error: The net clk is driven by more than one driv

a few things ...

1) It sounds like your clock is not tracing through your pad model. Check the .lib model of the pad to see if a) pin C is an output abd b) through is an arc from PAD -> C. Look for pin PAD then look for related_pin C.

2) For CTS you can define your clock root at the output of the pad cell to the core (pin C) like this:

## AutoCTSRootPin clk <- change this to below
AutoCTSRootPin IOCELL42/C

3) If you still can't get the clock to trace through the pad cell for timing, you can redefine your clock at the C pin of the pad cell (in your SDC). But this isn't fully correct as your IO timing will be off.

Added after 2 hours 42 minutes:

Greatrebel said:

PRUW1216SCDG_25 IOCELL42( .I(1'b0),.DS(1'b1),.OEN(1'b1),.PAD(clk),.C(IO42),.PE(1'b1),.IE(1'b1));

Click to expand...

ignore my last post for now and try this first ...

check the meaning of all the pad inputs you have tied off. You may be disabling the input (ex. OEN might need to be tied to 1'b0 instead of 1'b1)

Re: A CTS error: The net clk is driven by more than one driv

Hi shelby,

I checked the lib for I/O, C is the output, pad is the inout. From the datasheet, OEN is output disable as 1, IE is input enable as 1 for input path pad->c. I made the change AutoCTSRootPin IOCELL42/C, but still there is not timing.

For changing the clk to IOCELL42/C in sdc,
I changed clk in
create_clock -name "global_clock" -add -period 10.0 -waveform {0.0 5.0} [get_ports clk] to IOCELL42.C or IOCELL42/C. But this port can not be recognized. I am not sure whether SDC format supports hierarchical port name.

Thank you very much

Changing the AutoCTS pin is for building the clock tree not timing. Try re-running CTS now and see if it builds the tree correctly

For timing, you need get_pins on an internal pin instead of get_port.

create_clock -name "global_clock" -add -period 10.0 -waveform {0.0 5.0} [get_pins IOCELL42/C]

Re: A CTS error: The net clk is driven by more than one driv

Hi

Once I changed the SDC for create_clock -name "global_clock" -add -period 10.0 -waveform {0.0 5.0} [get_pins IOCELL42/C], I got the timing analysis. I can see the clock tree displayed after CTS if AutoCTSRootPin is changed to IOCELL42/C.

But I still do not know why I can not get the timing analysis when using clk pin

Thanks a lot for your help

Re: A CTS error: The net clk is driven by more than one driv

i think the issue is in the pad cell .lib file. Check it again to be sure there is an arc from pad -> c. Look for sdf_condition in the arc to double check your pad cell tie offs are correct.

You can also try the following to see the arc

report_delay_calculation -from IOCELL42/PAD -to IOCELL42/C

(not 100% sure this command works in encounter, if not look for a similar cmd)

Re: A CTS error: The net clk is driven by more than one driv

I copy the true table for the I/O pad following.

INPUT OUPUT
DS OEN I PAD PE IE PAD C
0/1 0 0 - 0/1 0 0 0
0/1 0 0 - 0/1 1 0 0
0/1 0 1 - 0/1 0 1 0
0/1 0 1 - 0/1 1 1 1
0/1 1 0/1 0 0/1 0 - 0
0/1 1 0/1 0 0/1 1 - 0
0/1 1 0/1 1 0/1 0 - 0
0/1 1 0/1 1 0/1 1 - 1
0/1 1 0/1 Z 0 0 - 0
0/1 1 0/1 Z 0 1 - X
0/1 1 0/1 Z 1 0 H 0
0/1 1 0/1 Z 1 1 H H

I checked the lib for pin C

pin(C) {
direction : output;
output_signal_level : CORE_VOLTAGE;
function : "IE * PAD";
timing() {
timing_sense : positive_unate;
related_pin : "PAD";
cell_rise( tpdn90lpnv2_CHAR_LIB_TABLE_CORE_LOAD_5x6 ) {
values("0.6132, 0.6175, 0.6214, 0.6301, 0.6577, 0.6824", \
"0.6358, 0.6401, 0.6439, 0.6526, 0.6804, 0.7050", \
"0.6399, 0.6441, 0.6481, 0.6568, 0.6845, 0.7092", \
"0.6225, 0.6269, 0.6308, 0.6395, 0.6674, 0.6919", \
"0.5554, 0.5597, 0.5637, 0.5725, 0.6004, 0.6250");
}
.....
pin(PAD) {
direction : inout;
input_signal_level : IO_VOLTAGE;
output_signal_level : IO_VOLTAGE;
...
The pin description is too long, can not paste them all here.

when I typed reportDelayCalculation -from IOCELL42/PAD -to IOCELL42/C

I got an error
**ERROR: (SOCDC-1628): No arcs from pin IOCELL42/PAD to pin IOCELL42/C.

I am not sure whether it is because the voltage, for pin PAD, it needs I/O voltage. In my netlist, I instanciated a I/O voltage cell
PVDD2POC_25 VDDPST_IO ( .VDDPST25());
I did not connect the pin of this cell to anywhere, because there are only I/O pads needing I/O voltage in my design. I think all the I/O pad are abutted together for getting the power. I do not know whether this I/O voltage causes the problem.

Thanks a lot

Added after 4 hours 36 minutes:

Hi shelby,

I fixed the problem already. It was because I did not load I/O timing lib. Sorry for this stupid mistake.

Thank you very much anyway