capitan
Newbie level 5
![Newbie level 5](/styles/images/ranks/blevel2.gif)
Hello,
I'm stumbling on this register behavior on my project.
**broken link removed**
The code for the register is this
The rising clock edge is right on the transition from 0 to 3 on the d signal. I'm using xilinx 11.5 webpack with ISim. Is this normal? I was expecting 3 to be passed to q right where 7 is and 7 to be passed to q on the next cycle...
I'm stumbling on this register behavior on my project.
**broken link removed**
The code for the register is this
Code:
architecture Behavioral of regn is
begin
process(Clk)
begin
if(Clk'EVENT and Clk='1' and WrEn='1') then
Q<=D;
end if;
end process;
end Behavioral;
The rising clock edge is right on the transition from 0 to 3 on the d signal. I'm using xilinx 11.5 webpack with ISim. Is this normal? I was expecting 3 to be passed to q right where 7 is and 7 to be passed to q on the next cycle...