vivek_p
Advanced Member level 4
I want to analyze the power of a design using Synopsys Design Compiler(DC).
1) First I set the Synopsys libraries
2) Read verilog files
3) Compiled the design
4) Checked the power (using "report_power" command)
5) Created the clock and set constraints
6) Once again compiled the design
7) Checked the power (using "report_power" command)
In the 4th step I got the power of the entire design to be 1.1 mW
In the 7th step I got the power of the entire design as .5 mW
The 7th step gives the clock power, then what does power in step 4 refer to?
Can anyone help me to find the power of the design using DC......
And one more thing I can only find the Dynamic power of the design , how can I get the leakage power
1) First I set the Synopsys libraries
2) Read verilog files
3) Compiled the design
4) Checked the power (using "report_power" command)
5) Created the clock and set constraints
6) Once again compiled the design
7) Checked the power (using "report_power" command)
In the 4th step I got the power of the entire design to be 1.1 mW
In the 7th step I got the power of the entire design as .5 mW
The 7th step gives the clock power, then what does power in step 4 refer to?
Can anyone help me to find the power of the design using DC......
And one more thing I can only find the Dynamic power of the design , how can I get the leakage power