vivek_p
Advanced Member level 4
I have two identical units in my design
I have designed a module "design.v"
I have also created two instances of design d1 and d2.
design d1 (ports lists);
design d2 (port lists);
design contains instantiation of lot of sub-modules and a memory module.
But in design d1 and d2 the memory module should be initialized with different values (Memory architecture is the same).
All other modules are the same.
How can I do the initialisation withour renaming the blocks and making two copies
design1 d1(ports lists); // renaming the blocks
design1 d2(port lists);
Can anyone help me in solving this issue..........
I have designed a module "design.v"
I have also created two instances of design d1 and d2.
design d1 (ports lists);
design d2 (port lists);
design contains instantiation of lot of sub-modules and a memory module.
But in design d1 and d2 the memory module should be initialized with different values (Memory architecture is the same).
All other modules are the same.
How can I do the initialisation withour renaming the blocks and making two copies
design1 d1(ports lists); // renaming the blocks
design1 d2(port lists);
Can anyone help me in solving this issue..........
