Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Difference between Verilog and SystemVerilog

Status
Not open for further replies.
W

whitchurch85

Junior Member level 2
Junior Member level 2
Joined
Mar 9, 2010
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
US/India
Activity points
1,430
I was going through a SysemVerilog primer, the syntax of both Veriog and SystemVerilog look the same.

What is the difference between both?
 

Syntaxwise SV is backward compatible with verilog. But SV has a lot of new features like classes, interfaces, OOPS concepts, etc.
 

There are lot of differences in verilog and SV.

we can say, SV= verilog+ all features required for Verification +assertions.

we have enhanced version of fork-join which is very usefull for parallel processes,
oops, inter-process communications [semaphore and mailboxes] and
also we can define functional coverage which helps in coverage metrics.

Once, if we start SV we can feel the thrill of it.

--Mahesh.
 

System Verilog is mainly used for testing and verification. It has constructs similar to Object oriented Programming

Verilog is mainly used for coding designs........................
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top