Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Connection of body of nwell resistor in layout in cadence

Status
Not open for further replies.
P

Peter_Dn

Newbie level 2
Newbie level 2
Joined
Mar 8, 2010
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Singapore
Activity points
1,295
Connection of body of nwell resistor in layout in cadence
For layout of nwell resistor in cadence, how should the substrate be connectted? what kind of contact should I use? Or, what is the material that forms substrate of nwell resistor? The process I am using is charted 0.18um process. Thanks a lot.

Regards
Peter
 

Re: Connection of body of nwell resistor in layout in cadenc

Peter_Dn said:
Connection of body of nwell resistor in layout in cadence
Click to expand...
Connect it to VDD resp. to the most positive potential.
 

Re: Connection of body of nwell resistor in layout in cadenc

Peter_Dn said:
Connection of body of nwell resistor in layout in cadence
For layout of nwell resistor in cadence, how should the substrate be connectted? what kind of contact should I use? Or, what is the material that forms substrate of nwell resistor? The process I am using is charted 0.18um process. Thanks a lot.

Regards
Peter
Click to expand...

Since you are using n-well resistor, it is laid-out directly to psub/pwell. Ptap should be put around the resistor inside the psub/pwell and should also be connected to vss. Same rule as other n-type devices is applied.
 

Re: Connection of body of nwell resistor in layout in cadenc

Hi!

I'm trying to do an nwell resistor in umc 0.18um.

Could someone tell me how to do it? I think I have to use a Twell but I'm not sure, and if I have to, I don't know exactly which layers do i have to use, and how to biasing them

Thanks!
 

Re: Connection of body of nwell resistor in layout in cadenc

As protonixs point out in a P-epi or P-substrate process the body is PEPI or PSUB so can not connected to anything. Only if you using a parasitic substrate resistance extraction there could be local connection to sub_layoutcellinstance. But this is typical handled in advanced design enviroments by the tools. So as a designer you do not have acces to the body terminal.

For a Triple-Well process there could be a PWELL-resistor in a NWELL. In this case the body is the NWELL and should/must be connected to a higher potential than any resistor terminal.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top