Opamp design for Pipelined ADC?

What all requirements should i meet that i can design an op-amp for 10 bit pipelined ADC? I am using switched capacitor circuits in my residue amplifier.

My VDD is 1V and am using 90 nm technology ?
I am planning to use a folded cascode op-amp without CMFB? Is CMFB important?
I am looking for a gain of 5000 and a PM of 60.
WHere can i find a step by step approach of designing such an op-amp?
My input is at 10Mhz and I plan to sample at 25 Mhz for my pipelined ADC.

What about the sample and hold circuit?
Please help

Hi Jennisjose,

The design of such amplifier is not simple, you will have a lot of work, but it is possible. Gain, bandwidth, noise, low-offset voltage and linearity are important parameters. The value of these parameters will depend on the specification of your ADC: ENOB, SINAD, SNR, etc, and also of your corners requirements.

In my option, common mode feedback is fundamental in this design. I`m not sure, but I would suggest you to increase the sampling frequency. I`m saying this because I worked with 10-bit pipelined ADC, and I used 40 MHz as sampling frequency,

Have you already chosen your architecture? Maybe 1.5 bit per stage, it is a good option.

The reference that I used to design my circuit is: `Design for Reliability of Low-voltage, Switched-capacitor Circuits” by Andrew Masami Abo.
There you will find many information you are looking for. Ok?
You must only write this in google, and you will find the reference.

Regards,

Hi palmeras thank you....
I am making 2 stage opamp with 1st stage as folded cascode and 2nd stage as a current source amplifier. I am getting a gain of 65 db and unity bandwidth of 900Mhz. This is 90 nm technology and I have 1V VDD. I am attaching the circuit that i am using . I am trying to get my phase margin to 60 degrees but I am not successful as my circuit is oscillating. What kind of compensation should i try?
Is there anything wrong with my compensation that i m doing this way?

The value of resitance is 2K and C is 50 f?
I don't know how to design compensation? I am just intuitively substituting diffrent values for compensating? Please Help

with a carefully designed 1-stage folded cascode, you can achieve about 70-75dB (not far from what you need) and you could use gain boosting to gain some margin. In this case you have the advantage that you need no compensation.

If you want to design a 2-stage opamp, try to read "An improved frequency compensation technique for CMOS operational amplifiers " Ahuja, B.K. Solid-State Circuits, Dec 1983.

But my problem is because i need a 20MSPS i need a gain bandwidth( 3db frequency of opamp) to be around 30MHz. I have only 1 V rail to rail supply.
I designed my opamp with input rail to rail diffrential folded cascode opamp and 2nd stage as common source stage. I also added a CMFB circuit.

BUt I am getting a open loop gain of 54db, and a Phase margin of 45. And unity gain bandwidth (GBP) of 500Mhz.
My tail current is 100uA and my 3db frequency is 1Mhz.
How do I increase my 3dB frequency to 30Mhz????




I am not showing the CMFB circuit. My tail current is 100uA and technology is 90nm? The CMFB voltage is 500mV.

jennisjose said:

BUt I am getting a open loop gain of 54db, and a Phase margin of 45. And unity gain bandwidth (GBP) of 500Mhz.
My tail current is 100uA and my 3db frequency is 1Mhz.
How do I increase my 3dB frequency to 30Mhz????

Click to expand...

I am sorry I do not understand what you need to do: you want to achieve a bandwidth of 30MHz and a gain of 5000 with 60deg phase margin? Are you sure you have the correct specifications for your amplifier???

The design of my Masters project operational amplifier is uploaded here. I have a gain of 71 db, PM of 45, and bandwidth of 700Mhz.

https://jennisjose.webs.com/operationalamplifiers.htm