what is the Vd(sat) parameter

Hello all,my question is : what is the Vd(sat) parameter in cadence spectre simulation results??Is the Vds that a cmos transistor must have in order to enter the saturation region and it means that a designer must be carefull to have Vds=Voverdrive + Vdsat for nmos transistors to operate in sat region??

A second question is : Can somebody explain to me why do we bias the input and the output of an opamp at Vdd/2 point (assuming Vss=0) expect from expecting max ouput swing?If we choose another bias point is it wrong and if the bias points of input and output are different is unacceptable?

Any helpful answers would be appreciated.Thanks in advance.

Hi jimeece13, I will try to answer to your second question:

Can somebody explain to me why do we bias the input and the output of an opamp at Vdd/2 point (assuming Vss=0) expect from expecting max ouput swing?If we choose another bias point is it wrong and if the bias points of input and output are different is unacceptable?

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Any op-amp has a certain range in which the common mode of the inputs should be maintained. You are not absolutely needed to keep this exactly at Vdd/2 (if you are using a single supply, of course), but this point is a good choice since probably your op-amp is optimized to work in this point.
What does that mean exactly?
Well, it depend on your particular op-amp.
Some will degrade their performances gradually when reaching the border of the allowed input common mode region and then they will become practically unusable. Others (such as Rail to Rail models) have been optimized to work very well in a very large common range, which in practice includes your Vss and Vdd limits (and even a little bit more).
Be careful. In some cases (such as with the otherwise very polite TL081 and similars), you can experience unexpected phenomena of phase reversal of the output if you exceed the allowed input common mode range. This can be just a disaster if you are working in a control loop. Have a look for example to:
https://www.analog.com/static/imported-files/tutorials/MT-036.pdf


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Before i pose my next quetions,first i must say thanks for your help DarwinNE.

So,the conclusion for biasing the input transistors of the first stage is to keep the common mode dc biasing voltage at vdd/2 levels so as to be safe from performance degradation due to the reasons you mentioned?did i get it right?doc you sent also helpful.

What about the output dc voltage?What are the benefits at the vdd/2 point except from having optimized output swing?

Before i pose my next quetions,first i must say thanks for your help DarwinNE.

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My pleasure

So,the conclusion for biasing the input transistors of the first stage is to keep the common mode dc biasing voltage at vdd/2 levels so as to be safe from performance degradation due to the reasons you mentioned?did i get it right?

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Yes, even if normally you have a certain degree of freedom when choosing the bias point. Your op amp must meet its specifications in term of bias current, offsets, open loop gain and so on for the entire range of the allowed input common mode range. Some characteristics can be better than the declared specs somewhere, and probably Vdd/2 is one of the best choices. This really depends on the particular op amp, since it depends on the typical application for which it has been optimized.
A few years ago, I measured the input offset of a few TL081's (biased at Vcc/2), finding performances which are almost 10 times better of those declared. This is normal since the fab normally takes a certain margin to cope with temperature change and statistical variations. It would be nice to see how a parameter such as the input offset is dependent on the bias point. I will try a day or another

Added after 1 hours 41 minutes:

I missed the last question...

What about the output dc voltage?What are the benefits at the vdd/2 point except from having optimized output swing?

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The situation is similar to the input. Probably, at Vdd/2 your output stage will have the best performances. Anyway, there are wonderful R2R op amps whose output can practically touch Vss and Vdd, with interesting currents.

Your answer are very helpful and i have to thank you again ofcourse

I am wondering about all these things that concern the biasing of the in/out of an opamp because these days i have come up with my first low power (low power supply-that is Vdd=1.2V,Vss=0) opamp design.So for a 90nm design kit i have the problem of biasing all of the transistors of my first stage that is a folded cascode OTA with the diff pair transistors to be pmos.

I have made a choise to divide my Vdd by 4 so as to give Vds=300mV to each of the 4 transistors of the folded cascode.Also i decided to have an overdrive voltage Vgs-Vth of about 100mV and a Vds=Vod + 200mV (the 300mV i mentioned before) in order to work in strong inversion...But i am not pretty sure if the limits i have chosen are proper for the strong inversion conditions.I would appreciate your opinion at this point.I am also thinking if i take out one transistor of the folder cascode (nmos or pmos) would it be right?Under this thought my dc output voltage will not be Vdd/2 assuming equal division by 3 of my Vdd.

And a last point that is important to me,have you ever come up with this damn Vdsat parameter under spectre simulator of cadence virtuoso?I have read a lot about it but i can't get a clear answer to my problem...I have two ideas.At first i suppose that it is the Vod=Vgs-Vth (spectre results seem to agree since the two parts of this equation have a difference of some mV).My second idea is that it is the quantity of voltage that Vds must be upper than Vod,that is : Vds=Vod+Vdsat.

Thanks in advance!

My experience is mainly in analog discrete circuits. Since I will have to work in analog integrated design within a few months, I will try to answer to your questions, but I hope someone more experienced than me in the field will correct me, if I say nonsenses...

I am wondering about all these things that concern the biasing of the in/out of an opamp because these days i have come up with my first low power (low power supply-that is Vdd=1.2V,Vss=0) opamp design.So for a 90nm design kit i have the problem of biasing all of the transistors of my first stage that is a folded cascode OTA with the diff pair transistors to be pmos.

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Woha, probably not the easiest piece of silicon around... There are several strategies in order to decide how to proceed in the design. In my point of view, you should first specify very clearly your specs. You should know if your want to optimize noise, power consumption, slew rate, DC voltage gain, precision, CMRR...

1 - In a OTA, I would probably begin by choosing a particular bias current for the tail of the differential pair. This should be chosen in order to cope with the speed and slew-rate specs. Of course, if you have power consumption limits, you should be careful when choosing bias currents...

2 - I would determine the inversion level for the differential pair transistors. Working at weak inversion reduces the offset between the two transistors and increases the transconductance, while working at strong inversion increases speed as well as thermal noise. A good compromise can be the moderate inversion.

3 - I would design the load with folded pair.

4 - I would treat the cascode load. The inversion level of the transistors often determine the output range allowed.

5 - Only now, I will bias all the transistors (voltage and current).

The procedure I described is suggested in D. Stefanovic, M. Kayal "Structured Analog CMOS Design" (Springer, 2008), but there are other good books out there in which you can study the details. You should pay attention to the transistor model you are using, since it needs to be good in moderate as well as in strong inversion.

And a last point that is important to me,have you ever come up with this damn Vdsat parameter under spectre simulator of cadence virtuoso?I have read a lot about it but i can't get a clear answer to my problem...

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I do not use Cadence Virtuoso, so I can just guess what it can be. The V_DSsat symbol can mean a design parameter which is the saturation voltage. It is the limit between the region of characteristics in which the drain voltage has an influence on the drain current (triode region) and the region in which the drain voltage plays an almost negligible role in the drain current. Once the bias current is known, this parameter depends on the inversion level of the transistor and it increases with him. Just my two cents.[/code]

thanks dude,i appreciate your opinion and and your answers one more time