conditional hardware generation in VHDL

HI all,



I just wanted to know how hardware is generated by VHDL conditionally.
Conditionally means depending upon the parameters receives from its top module.

Regards

Dear Raghavca,

I'm not sure about what you are asking. Do u mean that some H/W aren't generated if its condition is not satisfied, something like a simple vhdl code for a multiplexor:

architecture a1 of some_entity
begin
{
process(in_A,in_B,in_Sel)
begin
if in_Sel =1 then
out_C = in_A;
else
out_C = in_B;
end if
end process;
}
end a1;

You think that if "in_Sel" is always '1' the H/W generated will not include the case for out_C =in_B. Yes, the synthesizer has optimizer which do that.However, it is not easy to know which H/W was generated without a synthesis tool. I mean that you have to view the design after translation, mapping, place and route.
But this is not a good design methodology espicially for large designs.

It is better to know that efficient design entry should not have such a situation, because if you know apriori that the second case will not happen, then use a latch not a multiplexor.

More generally, if you your design entry is decribed in RTL level, you will not face that problem, because you will be using basic logic elements only. You need to check the synthesizer output if your design entry is at the algorithmic or beahviour level.

Best Wishes,
Sameh Yassin

By top-level "parameters" do you mean generics?

You can use generics or constants in a generate statement. Which is an explicit way to conditionally create logic, (rather than implicit thru a compile-time constant signal that gets optimized out by synth.)


You will need to pass down top level generics through your hierarchy as generics for each component. They aren't global, just like you'd have to pass down ports. And unlike if-then-else there is no else for generates, you will need to have a second statement.

HI ,

Thanks for rush of answers.
I mean, in verilog we have some compiler directives like 'ifdef, 'define.

Ex: 'define max 1
// 'define min 1

'ifdef max
//body
'endif

'ifdef min
//body
'endif


This I wanted to develop in VHDL. I have give straight forward problem to you.

Expecting answers.

Regards

That's exactly what the generate construct is for. It is not inside a process like an if-then statement but stands alone inside the entity body. ( you can have a body only and no local signals and even omit the "begin" in that case.)

Besides generate, you can consider any expression, that is constant at compile time for conditional hardware generation. That's important, because generate can not be used inside a sequential block (a process). But the "code" inside an always false IF THEN .. END IF block is effectively treated like an inactive GENERATE block, because the design compiler completely removes it.

You may get a compiler warning about always false IF condition.

As a general comment, I notice, that you are asking a lot of VHDL questions, that could be probably answered more effectively by a good VHDL text book.

Hi TA37,

Thanks for your answer.

HI FvM : Yeah I have been asking so many VHDL syntax questions rather than some logical. Its because of time constraint and understanding proble as I am new user for that. But actually I shouldn't.

Thanks guys

Is there any directives for the synthesizer to accomplish the same job?
--
Amr Ali

your synth tool may have its own custom ones too, but that is bad for portability. I'd recommend against these directives if at all possible as they can cause simulation to not match hardware. Usually they are a sign of sloppiness. (I've used them when I was too lazy to make/find a behavioral model of a tech specific buffer black-box.) And dangerous if one line gets deleted/moved.