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PLL multiplication of variable frequency input

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maame

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Hi all,

I'm in a fix about something here. I want to design a pll circuit that multiplies a varying frequency reference signal by 12. It is actually a square wave but not with a constant frequency. They are supposed to correspond to pulses (attached a figure of what I mean). Now my question is, will it work? I mean if the input is not a constant frequency signal how do I get the PLL circuit to work? Any ideas?

Secondly, if it works, will the pll output the square wave frequency × 12 or will it just multiply each pulse by 12 and output.

Lastly, can I put a switch on the PLL via 555 timer to switch it on and off at defined periods?

Thanks. I hope I made my question clear.
 

A PLL is defined by the eq :

Fout = Fref*N ; let N=12; So you are good there!

Now the out put of the PLL is a Sine wave(Assuming you have a VCO), is that
your case?
Or are you talking about a DPLL or ADLL?(Google these for more info)

For the analog type you should be fine as long as your Ref Freq does not change
faster than the PLL's "step" and or "lock" times.

Hope this helps
 

    maame

    Points: 2
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Thanks Element_115 for replying to my post. Actually, it is a square wave input I'm looking at. It is a comparator representation of pulses which vary in frequency, making the square wave vary also in frequency. I have a sample of the input signal attached to my earlier post.

And for DLL or ADLLs, I have no time to work them out. I have to get this done and present it very soon. I can easily get components for the PLL but not the DLL because of where I am.

Thanks again. Hope to hear from you soon.
 

understood your question:

yes your PLL will provide multiplication of frequency crossponding to input variable frequency.

But the lock time is limitation.

You will not be able to get exact multipication if the locking time of your PLL is more than the time of frequency hop from one frequency to the next.

If you need continously varying inputfrequency multiplication than forget about PLL because PLL need locking time to crosspond and repond to new frequency.

right
 

    maame

    Points: 2
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