Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

frequency divider for PLL

Status
Not open for further replies.

manikandanmadurai

Newbie level 2
Newbie level 2
Joined
Feb 6, 2010
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
sweden
Activity points
1,302
Hi,

i have to design a "programmable frequency divider" for pll(to be used as bfsk). the VCO output is 400 and 420 MHz. reference input is 10MHz.the divider N values are then 40 and 42..

1. pls help me with some links that would be useful for my prestudy

2.which architecture is recommended

3. what does "programmable" actually means

4. i shud start with behavior modelling(verilog-a)..need some references

CMOS 0.35u process
 

Hi,
I think a better PLL datasheet helps lot of _with circuits ideas/apps. too...
Check pls. products of firms as Fujitsu, Nec, Mr. Rohde`s books over "high quality PLL_Synthesizers"...
k.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top