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Decap cells are basically capacitors used for decoupling.
The gates in a circuit consume most power (dynamic) only at the clock edges. No voltage source is perfect hence glitches are produced on the power line due to huge current draw at the clock edges.
Decap filler cells are small capacitors which are placed between vdd and ground all over the layout. all these small capacitors add up to a big capacitor between vdd and ground. This helps to smoothen out the glitches. Apart from decap fillers , decap macros are also placed in a big design to give additional decoupling.
Decap calls r used to reduce the power bounce only (as i know).
decap cell contains Nmos Transisitors only just it acts like a reserviour .
this decap cell is charged to VDD if any power bounce occurs it gives the sufficient required voltage 4 the Cells which r placed after that Decap cell
Ground bounce is reduced by placing the more Ground I/O pads than Power pads
i dont know how it reduces the Ground bounce if any body knows explain it clearly
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