how to develop standard cell library with cadence tools

can any one tell me how many kinds of files does the standard cell library has and how to get these get these files with cadence tools ? and telling me which cadence tools will be used when developing standcell library will be better,
thank you in advance,

Hi changxiaolong,

I know Cadence SignalStorm can do this. You can maybe start with this tutorial:
http://www.chiptalk.org/modules/wfsection/article.php?articleid=15

I hope this helps.

regards

thanks for yourhelp .i have tsmc 180nm standard cell library and arm ip.but i don't know how to use their information to design digital ic with tools 'can you give some advance thank you newbie

Added after 3 minutes:

with cadence tools
thanks newbie

so let's answer some question so I know, what you want to do to give you the right hints.
Your task is to use a tsmc standard lib and an arm IP to design a digital design, isn't it? So you doesn't need to characterise a lib, you have this lib and want to use it, right?
The 2nd thing: Do you want to generate the netlist by hand, this implies choosing digital gates and put them together in a schematic or do you want to describe your function in a hardware description language (HDL), like VHDL or Verilog, and synthesize it (I know synopsys design compiler can do that, I've forgotten how cadence calls this tool).
It will be the best thing you decribe your task a little bit more in detail.

regards

hello newbie, I was busy last two days, so let's me answer your question now.
The first question : yes, i want to design a digital circuit with tsmc standard cell lib and arm IP, and I also need design some special gate such as nand,nor,inverter which can meet my needs with tsmc PDK. these special gate will be used when I design my digital circuit just like the tsmc standard cell lib. so perhaps ,i also need to characterise a lib and other information needed.
the 2nd question: I want to describe my circuit with hdl language and then synthesize it with tools

perhaps i need some tools to design analog circuit . can you give me some docs or exams or advice so that i can follow.
wish you answers
thank you very much!!!

ok I see there's much to explain . I think I give you a short digital design flow overview, with some links to useful tutorials.
1st you need your HDL description:
I used verilog and vhdl. For both languages I can recommand you the book Douglas Smith - HDL Chip Synthesis. Unfortunately this book is sold out. Maybe your local library can help you... It provides many examples and shows the generated netlists. For vhdl Peter Ashendens The Designers Guide to VHDL is useful, too. Your description can be simulated with Cadence NC-Sim and the results can be shown by Cadence SimVision. You have to asked your colleagues form the IT department for setting up the environment. If this isn't a solution I've to write you a start-up script. To check your code at this point there are some useful tools. I sometimes use Synopsys Leda Design Rule Checker. I'm sure, Cadence has a similar solution

The second tool you need is a Compiler, which converts your HDL description to a netlist. I usually use Synopsys DesignCompiler. But I also know Cadence RTL Compiler can do this. I hope this tutorial helps:
**broken link removed**
At this point you also need some scripts. For example to set the tech libs. Hope you can get some help. Otherwise I play a little bit with our tsmc lib (if you are planing to use 180nm lib) or provide you a general script. As I mentioned I usually use Synopsys DC, maybe somebody else can help you with a script for Cadence RTL Compiler.
At synthesis level you can generate a sdf-File (standard delay format). This can be used for simulation to account for delays of the gates. You again simulate the netlist using ncsim and simvision.

The third main step is the physical implementation. This step is done by Cadence SOC Encounter or EDI (as it is called in the newer versions) and generates a layout for you. Main steps are floorplanning, power planning, placement, clock tree synthesis (CTS), routing and filler. But there are a plenty of further options. If you reach this point, I'll think we discuss again
The result of this step is a NEW netlist (because clock tree and buffers are added) and again a new sdf file. And...... right a simulation again.

Hopefully I've forgotten nothing important.

regards


by the way, my nickname is ddet2004 and not newbie. this is my status because I registered short time ago

yes i am a new member too, i have seen the website you give me ,it's helpful .and your descreption make me know the design flow clearly,
would you mind telling me your name and e-mail ?
it deosn't matter,if you don't want to do that

thank you so much

you can contact me here in the forum via a private message. just click on the pm button at the end of one of my posts.

regards