Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
##
## Run after elaboration
##
set_fix_multiple_port_nets -all -buffer_constants
set verilogout_equation false
set verilogout_no_tri true
set write_name_nets_same_as_ports true
set verilogout_higher_designs_first false
set verilogout_show_unconnected_pins true
set hdlout_internal_busses true
set_fix_multiple_port_nets -all [get_designs]
set current_design digitalTop
##
## To write out netlist
##
change_names -rules verilog -hierarchy
write -format verilog -hier -output digitalTop.v
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
