About a Verilog code for digital Sigma-Delta modulator

sigma delta verilog

Hi,
I am design a ΣΔ fractional- frequency synthesizer, and I find a verilog code for the digitao sigma-delta modulator, which is a single-loop multi-bits quantizer. The output is 5bit and the input is 22Bits. Its structure and the verilog code are shown below. But when I simulate this verilog code, the result is not right.
The input word-width is 22Bits, and I want to get a fraction of 0.25, so I add an input of 0.25×2(22)=1048576. But when I calculate the average of the output to the total nunber of clock, it equal to 1.8.
Is there any matter with the code? And is there any different between the input of MASH and single-loop, in MASH, the input = fraction × the word-width.
Please give some advice.

Thank you!
Best regards!

structure


Verilog-code and testbench

Hi, do you have a updated version of the code? can you show me where you find the source code?
Many thanks

funny,
i just start learning delta-sigma stuff
maybe i will give an answer later

anyway, thx for the code!

take a look at my code,

i think it is correct

hi strennor,

I want to model a single-loop multi-bits sigma-delta modulator with VHDL. I read your code but i dont understand it because i know vhdl syntax only can you help me how can i translate it to vhdl code. thans a lot

Noura