hakihaki
Newbie level 3
Hi
I'd designed VCO using replica current bias(cascode current mirror).
But now I'll design a regulator(load current - 1~2mA) for improvement to VCO phase noise.
I have a question. Which is better VCO phase noise? Is it right that the regulator have VCO phase noise to be better?
Thanks
I'd designed VCO using replica current bias(cascode current mirror).
But now I'll design a regulator(load current - 1~2mA) for improvement to VCO phase noise.
I have a question. Which is better VCO phase noise? Is it right that the regulator have VCO phase noise to be better?
Thanks